1
Rod G Fleck, Venkat Mattela, Eric Chesters, Muhammad Afsar: Data processing device with loop pipeline. Siemens Aktiengesellschaft, July 4, 2000: US06085315 (75 worldwide citation)

The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a loop pipeline unit for processing a loop instruction having input and output stages, said input stages of ...


2
Andreas Wenzel, Eric Chesters, Rod G Fleck, Gary Sheedy: On-chip debug system. Infineon Technologies, Fish & Richardson P C, February 4, 2003: US06516428 (60 worldwide citation)

An on-chip debug system includes a data band selector operable to transmit to an emulator the selected data bands generated by the selected components in an integrated circuit. The data band selector is directed by the emulator based upon instructions received from a host computer.


3
Rod G Fleck, Roger D Arnold, Bruce Holmer, Vojin G Oklobdzija, Eric Chesters: Data processing unit with hardware assisted context switching capability. Siemens Aktiengesellschaft, October 3, 2000: US06128641 (36 worldwide citation)

The present invention relates to a method of context switching from a first task to a second task in a data processing unit having a register file with a plurality of general purpose registers and a context switch register, a memory comprising a previous context save area and an unused context save ...


4
Eric Chesters, Roger D Arnold, Rod G Fleck: Data processing unit with debug capabilities using a memory protection unit. Siemens, January 16, 2001: US06175913 (13 worldwide citation)

A data processing unit is described which comprises a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus. A debug unit is coupled to the bus, a protection unit is coupled with the bus and with the debug unit for ...


5
Klaus J Oberlaender, Ralph Haines, Eric Chesters, Dirk Behrens: Configurable embedded processor. Infineon Technologies, Dickstein Shapiro, October 26, 2010: US07821849 (7 worldwide citation)

A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification s ...


6
Balraj Singh, Eric Chesters, Venkat Mattela, Rod G Fleck: Reducing instruction transactions in a microprocessor. Infineon Technologies North America, Fish & Richardson P C, May 21, 2002: US06393551 (5 worldwide citation)

A method and an apparatus for reducing the number of instruction transactions in a microprocessor are disclosed. As a method, the number of issued instructions carried by an issued instruction bus in a computer system are reduced by determining if an instruction fetched by a fetch unit matches a cac ...


7
Klaus J Oberlaender, Ralph Haines, Eric Chesters, Dirk Behrens: Configurable embedded processor. Infineon Technologies, Dickstein Shapiro, March 4, 2008: US07339837 (4 worldwide citation)

A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification s ...


8
Klaus J Oberlaender, Ralph Haines, Eric Chesters, Dirk Behrens: Configurable embedded processor. Infineon Technologies, Dickstein Shapiro, September 18, 2012: US08270231 (2 worldwide citation)

A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification s ...


9
Klaus J Oberlaender, Ralph Haines, Eric Chesters, Drik Behrens: Configurable embedded processor. Infineon Technologies, Dickstein Shapiro, August 14, 2008: US20080195835-A1

A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification s ...


10
Andreas Wenzel, Eric Chesters, Rod G Fleck, Gary Sheedy: On-chip debug system with a data band selector. Siemens Corporation, October 10, 2002: US20020147939-A1

An improved on chip debug system is disclosed. The on chip debug system includes a data band selector arranged to selectively transmit particular data bands generated by a processor included in an integrated circuit as needed to an emulator. The data band selector is directed by the emulator based u ...