1
Ely K Tsern, Richard M Barth, Craig E Hampel, Donald C Stark: Power control system for synchronous memory device. Rambus, Gary S Williams, Pennie & Edmonds, March 2, 2004: US06701446 (117 worldwide citation)

A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the m ...


2
Richard M Barth, Ely K Tsern, Craig E Hampel, Frederick A Ware, Todd W Bystrom, Bradley A May, Paul G Davis: Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain. Rambus, Blakely Sokoloff Taylor & Zafman, November 28, 2000: US06154821 (115 worldwide citation)

A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memo ...


3
Ely K Tsern, Thomas J Holman, Richard M Barth, Andrew V Anderson, Paul G Davis, Craig E Hampel, Donald C Stark, Abhijit M Abhyankar: Memory device and system including a low power interface. Intel Corporation, Rambus, Pennie & Edmonds, April 23, 2002: US06378018 (113 worldwide citation)

A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power inte ...


4
Frederick A Ware, Ely K Tsern, Richard E Perego, Craig E Hampel: Method and apparatus for coordinating memory operations among diversely-located memory components. Rambus, Hunton & Williams, January 6, 2004: US06675272 (113 worldwide citation)

A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are c ...


5
Billy Wayne Garrett Jr, Frederick Abbott Ware, Craig E Hampel, Richard M Barth, Don Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J Sheffler, Ely K Tsern, Steven Cameron Woo: Memory module with offset data lines and bit line swizzle configuration. Rambus, Morgan Lewis & Bockius, January 4, 2005: US06839266 (94 worldwide citation)

A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.


6
Ely K Tsern, Richard M Barth, Craig E Hampel, Donald C Stark: Power control system for synchronous memory device. Rambus, Pennie & Edmonds, July 17, 2001: US06263448 (92 worldwide citation)

A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the m ...


7
Ely K Tsern, Ramprasad Satagopan, Richard M Barth, Steven C Woo: Memory controller with power management logic. Rambus, Morgan Lewis & Bockius, February 21, 2006: US07003639 (81 worldwide citation)

A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retri ...


8
Ely K Tsern, Richard M Barth, Paul G Davis, Craig E Hampel: Dram core refresh with reduced spike current. Rambus, Pennie & Edmonds, June 13, 2000: US06075744 (75 worldwide citation)

A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge curre ...


9
Frederick A Ware, Ely K Tsern, Craig E Hampel: Low power memory device. Rambus, Charles Shemwell, February 9, 2010: US07660183 (73 worldwide citation)

In a memory device having a memory core and a signal interface, receiving a command that specifies at least a portion of a memory access. During the memory access, transferring data between the memory core and the signaling interface, and transferring the data between the signaling interface and an ...


10
Ely K Tsern, Richard M Barth, Paul G Davis, Craig E Hampel: DRAM core refresh with reduced spike current. Rambus, Pennie & Edmonds, July 24, 2001: US06266292 (64 worldwide citation)

A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge curre ...