1
Katherina Babich
Katherina E Babich, Sean D Burns, Elbert E Huang, Arpan P Mahorowala, Dirk Pfeiffer, Karen Temple: Antireflective composition and process of making a lithographic structure. International Business Machines Corporation, Connolly Bove Lodge & Hutz, Daniel P Morris, February 5, 2008: US07326442 (6 worldwide citation)

An antireflective composition and a lithographic structure comprising a silicon-metal oxide, antireflective material derived from the composition. The antireflective composition comprises a polymer of formula I, wherein 1≦x≦2; 1≦y≦5; 1≧0; m>0; n>0; R is a chromophore, M is a metal selected from Grou ...


2
Katherina Babich
Katherina E Babich, Sean D Burns, Elbert E Huang, Arpan P Mahorowala, Dirk Pfeiffer, Karen Temple: Antireflective composition and process of making a lithographic structure. International Business Machines Corporation, Connolly Bove Lodge & Hutz, January 18, 2007: US20070015083-A1

An antireflective composition and a lithographic structure comprising a silicon-metal oxide, antireflective material derived from the composition. The antireflective composition comprises a polymer of formula I, wherein 1≦x≦2; 1≦y≦5; 1≧0; m>0; n>0; R is a chromophore, M is a metal selected from Grou ...


3
Matthew E Colburn, Elbert E Huang, Satyanarayana V Nitta, Sampath Purushothaman, Katherine L Saenger: Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence. International Business Machines Corporation, Daniel P Morris Esq, Harrington & Smith, August 16, 2005: US06930034 (18 worldwide citation)

A method for fabricating low k and ultra-low k multilayer interconnect structures on a substrate includes: a set of interconnects separated laterally by air gaps; forming a support layer in the via level of a dual damascene structure that is only under the metal line; removing a sacrificial dielectr ...


4
Daniel C Edelstein, Matthew E Colburn, Edward C Cooney III, Timothy J Dalton, John A Fitzsimmons, Jeffrey P Gambino, Elbert E Huang, Michael W Lane, Vincent J McGahay, Lee M Nicholson, Satyanarayana V Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M Shaw, Andrew H Simon, Anthony K Stamper: Device and methodology for reducing effective dielectric constant in semiconductor devices. International Business Machines Corporation, Joseph P Abate, Greenblum & Bernstein, July 29, 2008: US07405147 (16 worldwide citation)

A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template m ...


5
Elbert E Huang, Philip J Oldiges, Ghavam G Shahidi, Christy S Tyberg, Xinlin Wang, Robert L Wisnieff: MOSFET structure with ultra-low K spacer. International Business Machines Corporation, Gibb & Rahman, April 29, 2008: US07365378 (15 worldwide citation)

A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-lay ...


6
David V Horak, Elbert E Huang, Charles W Koburger III, Douglas C La Tulipe Jr, Shom Ponoth: Sealed air gap for semiconductor chip. International Business Machines Corporation, Richard M Kotulak, Hoffman Warnick, March 5, 2013: US08390079 (13 worldwide citation)

A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the cont ...


7
Daniel C Edelstein, David V Horak, Elbert E Huang, Satyanarayana V Nitta, Takeshi Nogami, Shom Ponoth, Terry A Spooner: Microelectronic structure including air gap. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Vazken Alexanian, October 16, 2012: US08288268 (9 worldwide citation)

A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced ele ...


8
Daniel C Edelstein, Matthew E Colburn, Edward C Cooney III, Timothy J Dalton, John A Fitzsimmons, Jeffrey P Gambino, Elbert E Huang, Michael W Lane, Vincent J McGahay, Lee M Nicholson, Satyanarayana V Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M Shaw, Andrew H Simon, Anthony K Stamper: Reducing effective dielectric constant in semiconductor devices. International Business Machines Corporation, Ian D MacKinnon, Roberts Mlotkowski Safran & Cole P C, March 6, 2012: US08129286 (8 worldwide citation)

Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic ...


9
Stephen M Gates, Elbert E Huang, Dimitri R Kioussis, Christopher J Penny, Deepika Priyadarshini: Air gap semiconductor structure with selective cap bilayer. International Business Machines Corporation, Alexa L Ashworth, April 5, 2016: US09305836 (8 worldwide citation)

A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer ca ...


10
Stephen M Gates, Jeffrey C Hedrick, Elbert E Huang, Dirk Pfeiffer: Patterning layers comprised of spin-on ceramic films. International Business Machines Corporation, Daniel P Morris Esq, Scully Scott Murphy & Presser, October 12, 2004: US06803660 (8 worldwide citation)

The present invention comprises a method for forming a hardmask including the steps of depositing a polymeric preceramic precursor film atop a substrate; converting the polymeric preceramic precursor film into at least one ceramic layer, where the ceramic layer has a composition of Si