1
Xavier Baie
Brent A Anderson, Xavier Baie, Randy W Mann, Edward J Nowak, Jed H Rankin: High mobility transistors in SOI and method for forming. International Business Machines Corporation, Mark F Chadurjian, Schmeiser Olsen & Watts, September 23, 2003: US06624478 (25 worldwide citation)

The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been ...


2
Xavier Baie
Brent A Anderson, Xavier Baie, Randy W Mann, Edward J Nowak, Jed H Rankin: High mobility transistors in SOI and method for forming. International Business Machines Corporation, Schmeiser Olson & Watts, William D Sabo, November 8, 2005: US06962838 (4 worldwide citation)

The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been ...


3
Xavier Baie
Brent A Anderson, Xavier Baie, Randy W Mann, Edward J Nowak, Jed H Rankin: High mobility transistors in SOI and method for forming. Schmeiser Olsen Watts, December 18, 2003: US20030232467-A1

The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been ...


4
Xavier Baie
Brent A Anderson, Xavier Baie, Randy W Mann, Edward J Nowak, Jed H Rankin: High mobility transistors in soi and method for forming. International Business Machines Corporation, Jack P Friedman, Schmeiser Olsen & Watts, July 31, 2003: US20030141548-A1

The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been ...


5
David M Fried, Edward J Nowak, Beth A Rainey, Devendra K Sadana: Fin FET devices from bulk semiconductor and method for forming. International Business Machines Corporation, Mark F Chadurjian, Schmeiser Olsen & Watts, November 4, 2003: US06642090 (300 worldwide citation)

The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while ...


6
David M Fried, William C Leipold, Edward J Nowak: FinFET layout generation. International Business Machines Corporation, John W LaBatt, Hoffman Warnick & D&apos Alessandro, December 9, 2003: US06662350 (239 worldwide citation)

A method and system for generating a set of FinFET shapes. The method and system locate a gate in an FET layout. The set of FinFET shapes is generated coincident with the gate. The method and system can further create a FinFET layout by modifying the FET layout to include the set of FinFET shapes.


7
Edward J Nowak, BethAnn Rainey: High mobility crystalline planes in double-gate CMOS technology. International Business Machines Corporation, William D Sabo, September 21, 2004: US06794718 (169 worldwide citation)

A MOS device with first and second freestanding semiconductor bodies formed on a substrate. The first freestanding semiconductor body has a first portion thereof disposed at a non-orientation orthogonal, non parallel orientation with respect to a first portion of the second freestanding semiconducto ...


8
Edward J Nowak: High-performance CMOS SOI devices on hybrid crystal-oriented substrates. International Business Machines Corporation, Gibb I P Law Firm, William D Sabo Esq, February 7, 2006: US06995456 (162 worldwide citation)

Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. The first-type transistors are on first portions of the substrate that have a first type of crystalline orientation and second-type transistors are on second portions of the subst ...


9
K Paul L Muller, Edward J Nowak, Hon Sum P Wong: Planarized silicon fin device. International Business Machines Corporation, H Daniel Schnurmann, Ratner & Prestia, June 26, 2001: US06252284 (150 worldwide citation)

An improved fin device used as the body of a field effect transistor (“FET”) and an improved process of making the fin device. The fin device allows for the fabrication of very small dimensioned metal-oxide semiconductor (“MOS”) FETs in the size range of micrometers to nanometers, while avoiding the ...


10
William F Clark, David M Fried, Louis D Lanzerotti, Edward J Nowak: Strained fin FETs structure and method. International Business Machines Corporation, Mark F Chadurjian Esq, McGinn & Gibb PLLC, October 21, 2003: US06635909 (146 worldwide citation)

A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structur ...