1
George Z Chrysos, Jeffrey Dean, James E Hicks, Daniel L Leibholz, Edward J McLellan, Carl A Waldspurger, William E Weihl: Apparatus for randomly sampling instructions in a processor pipeline. Digital Equipment Corporation, Jenkens & Gilchrist a professional corporation, December 7, 1999: US06000044 (74 worldwide citation)

An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and stat ...


2
George Z Chrysos, Jeffrey Dean, James E Hicks, Daniel L Leibholz, Edward J McLellan, Carl A Waldspurger, William E Weihl: Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline. Compaq Computer Corporation, December 19, 2000: US06163840 (60 worldwide citation)

An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A subset of the t ...


3
Edward J McLellan: Reducing stall delay in pipelined computer system using queue between pipeline stages. Digital Equipment Corporation, Arnold White & Durkee, June 28, 1994: US05325495 (54 worldwide citation)

A pipelined computer system employs a queue stage to receive the output of one pipeline stage when a stall occurs in the next stage or downstream of the next stage. This avoids stalling earlier stages of the pipeline. Subsequently, the pipeline advances through the queue, until a bubble occurs. When ...


4
Thomas B Brightman, Andrew T Brown, John F Brown, James A Farrell, Andrew D Funk, David J Husak, Edward J McLellan, Mark A Sankey, Paul Schmitt, Donald A Priore: Digital communications processor. Freescale Semiconductor, Gordon E Nelson, August 29, 2006: US07100020 (52 worldwide citation)

An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). T ...


5
Joel S Emer, Simon Steely, Edward J McLellan: Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted. Digital Equipment Corporation, Christopher J Cianciolo, August 3, 1999: US05933860 (44 worldwide citation)

A computer system including an instruction cache (I-cache) having a plurality of banks for storing a subset of data from memory is shown to include a prediction mechanism for predicting which bank of the I-cache contains the required data. A prediction value, including a sequential prediction hint a ...


6
George Z Chrysos, Jeffrey Dean, James E Hicks, Carl A Waldspurger, William E Weihl, Daniel L Leibholz, Edward J McLellan: Apparatus for sampling instruction execution information in a processor pipeline. Compaq Computer Corporation, Oppenheimer Wolff & Donnelly, February 27, 2001: US06195748 (35 worldwide citation)

An apparatus is provided for sampling instructions in a processor pipeline of a computer system. The pipeline has a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A subset of the fetched instructions are identified as selected instructions. Event, latenc ...


7
Edward J McLellan, Bruce A Gieseke: Content addressable memory having memory cells storing dont care states for address translation. Digital Equipment Corporation, March 30, 1999: US05890201 (35 worldwide citation)

A method of accessing a content addressable memory storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state, is disclosed. The stored information is compared with a one bit signal. A match is indicated when the one bit signal ...


8
Simon C Steely Jr, Edward J McLellan, Joel S Emer: System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction. Compaq Computer Corporation, Hamilton Brook Smith & Reynolds P C, June 27, 2000: US06081887 (28 worldwide citation)

A technique for predicting the result of a conditional branch instruction for use with a processor having instruction pipeline. A stored predictor is connected to the front end of the pipeline and is trained from a truth based predictor connected to the back end of the pipeline. The stored predictor ...


9
Edward J McLellan, Bruce A Gieseke: Content addressable memory having a pair of memory cells storing dont care states for address translation. Digital Equipment Corporation, David A Dagg, Denis G Maloney, Arthur W Fisher, October 22, 1996: US05568415 (23 worldwide citation)

A content addressable memory has a pair of single-bit memory cells together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state. Each of the memory cells has a pair of transistors. One of the transistors connects a common ...


10
Gilbert Wolrich, Edward J McLellan, Robert Yodlowski, Daniel Dobberpuhl: ALU with carry length detection. Digital Equipment Corporation, Cesari and McKenna, November 18, 1986: US04623981 (16 worldwide citation)

An ALU, performing selected operations on input operands in a predetermined clock cycle, uses means for detecting a carry propagation path greater than a predetermined number of consecutive bit positions to cause a stretching of the clock cycle. Since such a long carry propagation path is detected f ...