1
Zeev Cohen, Boaz Eitan, Eduardo Maayan: Method for programming of a semiconductor memory cell. Saifun Semiconductors, Eitan Pearl Latzer & Cohen Zedek, September 18, 2001: US06292394 (145 worldwide citation)

A method for programming an array having a multiplicity of memory cells. The method includes, per cell to be programmed, verifying a programmed or non-programmed state of the cell and flagging those of the cells that verify as non-programmed during one of the verify steps after having previously ver ...


2
Ilan Bloom, Eduardo Maayan, Boaz Eitan: Programming and erasing methods for a reference cell of an NROM array. Saifun Semiconductors, Eitan Pearl Latzer & Cohen Zedek, December 3, 2002: US06490204 (103 worldwide citation)

A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming said reference cell with small programming steps until ...


3
Ilan Bloom, Boaz Eitan, Zeev Cohen, David Finzi, Eduardo Maayan: Programming of nonvolatile memory cells. Saifun Semiconductors, Tower Semiconductors, Eitan Pearl Latzer & Cohen Zedek, May 28, 2002: US06396741 (103 worldwide citation)

A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed of a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and ...


4
Eduardo Maayan, Ran Dvir, Zeev Cohen: Mass storage array and methods for operation thereof. Saifun Semiconductors, Infineon Technologies Flash, Eitan Law Group, December 13, 2005: US06975536 (93 worldwide citation)

Apparatus including a virtual ground array, which includes memory cells connected in rows and columns to word lines and bit lines, respectively. The virtual ground array includes at least one block of data, and peripheral circuitry adapted to simultaneously access a plurality of subsets of the at le ...


5
Eduardo Maayan, Ron Eliyahu, Shai Eisen, Boaz Eitan: Method for operation of an EEPROM array, including refresh thereof. Saifun Semiconductors, Eitan Pearl Latzer & Cohen Zedek, October 21, 2003: US06636440 (62 worldwide citation)

A method for operating an electrically erasable programmable read only memory (EEPROM) array, the method including refreshing a threshold voltage of a bit of a memory cell in an EEPROM array, the threshold voltage being different than a previous threshold voltage, by restoring the threshold voltage ...


6
Eduardo Maayan, Yair Sofer, Ron Eliyahu, Boaz Eitan: Architecture and scheme for a non-strobed read sequence. Saifun Semiconductors, Eitan Pearl Latzer & Cohen Zedek, March 18, 2003: US06535434 (60 worldwide citation)

An architecture and method for implementing a non-strobed operation on an array cell within a memory array in which a reference unit is provided for emulating the response of an array cell during a desired operation, for example, a read, program verify, erase verify or other types of read operations ...


7
Eduardo Maayan, Ron Eliyahu, Ameet Lann, Boaz Eitan: Method for programming a reference cell. Saifun Semiconductors, Eitan Pearl Latzer & Cohen Zedek, June 24, 2003: US06584017 (57 worldwide citation)

A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference ...


8
Joseph Shor, Yair Sofer, Eduardo Maayan: Charge pump with constant boosted output voltage. Saifun Semiconductors, Eitan Pearl Latzer & Cohen Zedek, June 10, 2003: US06577514 (50 worldwide citation)

A charge pump regulator for providing a constant boosted voltage at the output of a charge pump includes: 1) a charge pump; 2) a clamping regulator; and 3) a clamping transistor. Certain preferred embodiments further include an auxiliary charge pump that provides a voltage above V


9
Ilan Bloom, Boaz Eitan, Zeev Cohen, David Finzi, Eduardo Maayan: Programming of nonvolatile memory cells. Saifun Semiconductors, Ethan Pearl Latzer & Cohen Zedek, December 7, 2004: US06829172 (47 worldwide citation)

A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and ...


10
Eduardo Maayan, Boaz Eitan: Symmetric architecture for memory cells having widely spread metal bit lines. Saifun Semiconductors, Eitan Pearl Latzer & Cohen Zedek, October 14, 2003: US06633496 (47 worldwide citation)

A memory array includes a first plurality of metal lines, a second plurality of diffusion bit lines and a third plurality of select transistors. There are more than two diffusion bit lines per metal bit line. The memory also includes a cell area formed of four segmented cell bit lines an even select ...