1
Ebrahim Zahir: System for context-dependent name resolution. Sun Microsystems, January 7, 1998: EP0817444-A2 (152 worldwide citation)

A context-dependent, multiply binding name resolution system. A name resolver is provided, connected to either a requester's system or a receiver's system, or both. Requests to a given service or domain name are resolved to the appropriate IP address. The intended recipient of the request is resolve ...


2
Ebrahim Zahir, Nishtala Satyanarayana, Van Loo William C, Chen Sun Den, Narad Charles E, Normoyle Kevin B: Method and apparatus for interrupt communication in a packet-switched computer system. Sun Microsystems, October 23, 1996: EP0738978-A1 (20 worldwide citation)

An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to th ...


3
Ebrahim Zahir, Van Loo William C, Nishtala Satyanarayana, Normoyle Kevin B, Coffin Louis F Iii, Narad Charles E, Kohn Leslie: Active power management for a computer system. Sun Microsystems, October 2, 1996: EP0735455-A2 (7 worldwide citation)

The present invention provides a method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems inter-connected to each other. In turn, each computer system has one or more modules. Each computer system of the computer ne ...


4
Van Loo William C, Ebrahim Zahir, Nishtala Satyanarayana, Normoyle Kevin, Lowenstein Paul, Coffin Iii Louis F: A writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system. Sun Microsystems, October 2, 1996: EP0735484-A1 (5 worldwide citation)

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two ...


5
Nishtala Satyanarayana, Ebrahim Zahir, Van Loo William C, Lowenstein Paul, Lee Sue Kyoung, Coffin Iii Louis F: A parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system. Sun Microsystems, October 2, 1996: EP0735485-A1 (5 worldwide citation)

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two ...


6
Ebrahim Zahir, Nishtala Satyanarayana, Van Loo William C, Normoyle Kevin, Lowenstein Paul, Coffin Louis F Iii: A transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system. Sun Microsystems, October 2, 1996: EP0735483-A1 (3 worldwide citation)

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one ...


7
Van Loo William C, Ebrahim Zahir, Nishtala Satyanarayana, Normoyle Kevin, Kohn Leslie, Coffin Iii Louis F, Narad Charles E: A parallelized master request class structure for interfacing a processor in a packet switched cache coherent multiprocessor system. Sun Microsystems, October 2, 1996: EP0735482-A1 (3 worldwide citation)

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two ...


8
Nishtala Satyanarayana, Ebrahim Zahir, Van Loo William C, Normoyle Kevin, Kohn Leslie, Coffin Louis F Iii: Packet switched cache coherent multiprocessor system. Sun Microsystems, October 2, 1996: EP0735486-A1 (3 worldwide citation)

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. All of the sub-systems inclu ...


9
Van Loo William C, Ebrahim Zahir, Nishtala Satyanarayana, Normoyle Kevin B, Kohn Leslie, Coffin Louis F Iii: Method and apparatus for flow control in a packet-switched computer system. Sun Microsystems, October 2, 1996: EP0735476-A1 (1 worldwide citation)

This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave int ...


10
Ebrahim Zahir, Nishtala Satyanarayana, Van Loo William, Normoyle Kevin, Kohn Leslie, Coffin Iii Louis F: Cache coherent computer system that minimizes invalidation and copyback operations. Sun Microsystems, October 2, 1996: EP0735480-A1 (1 worldwide citation)

A computer system is disclosed that reduces the occurrences of invalidate and copyback operations through a memory interconnect by disabling a first write optimization of a cache coherency protocol for data that is not likely to be written by a requesting processor.