1
Ricardo H Bruce, Rolando H Bruce, Earl T Cohen, Allan J Christie: Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage. BIT Microsystems, Stuart T Auvinen, December 7, 1999: US06000006 (555 worldwide citation)

A flash-memory system provides solid-state mass storage as a replacement to a hard disk. A unified re-map table in a RAM is used to arbitrarily re-map all logical addresses from a host system to physical addresses of flash-memory devices. Each entry in the unified re-map table contains a physical bl ...


2
Ricardo H Bruce, Rolando H Bruce, Earl T Cohen: Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers. Bit Microsystems, Stuart T Auvinen, October 13, 1998: US05822251 (129 worldwide citation)

A flash-memory system is expandable. Rather than directly connecting individual flash-memory chips to a controller, flash buffer chips are used. Each flash buffer chip can connect to four banks of flash-memory chips. Chip enables for individual chips in a bank are generated from an address sent to t ...


3
Ricardo H Bruce, Rolando H Bruce, Earl T Cohen: Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations. Bit Microsystems, Stuart T Auvinen, September 21, 1999: US05956743 (128 worldwide citation)

A flash-memory system adds system-overhead bytes to each page of data stored in flash memory chips. The overhead bytes store system information such as address pointers for bad-block replacement and write counters used for wear-leveling. The overhead bytes also contain an error-correction (ECC) code ...


4
Earl T Cohen, James S Blomgren, David E Richter: Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU. Exponential Technology, Stuart T Auvinen, July 14, 1998: US05781457 (100 worldwide citation)

A Boolean logic unit (BLU) features a vectored mux. Boolean instructions are executed by applying operands to the select inputs but truth-table signals to the data inputs. Merge and mask operations are performed by reversing the connection and inputting the operands to the data inputs but applying a ...


5
Srinivasa Rao Malladi, Earl T Cohen: Methods and apparatus for maintaining statistic counters and updating a secondary counter storage via a queue for reducing or eliminating overflow of the counters. Cisco Technology, The Law Office of Kirk D Williams, December 4, 2007: US07304942 (92 worldwide citation)

Methods and apparatus are disclosed for maintaining statistic counters and updating a secondary counter memory via a queue for reducing or eliminating overflow of the counters. Multiple counter values are stored in a primary counter storage. An indication of a particular counter to update is receive ...


6
Earl T Cohen, Russell W Tilleman, Jay C Pattin, James S Blomgren: Master-slave cache system for instruction and data cache memories. Exponential Technology, Stuart T Auvinen, August 27, 1996: US05551001 (68 worldwide citation)

A master-slave cache system has a large, set-associative master cache, and two smaller direct-mapped slave caches, a slave instruction cache for supplying instructions to an instruction pipeline of a processor, and a slave data cache for supplying data operands to an execution pipeline of the proces ...


7
James S Blomgren, Earl T Cohen, Brian R Baird: Block-based branch prediction using a target finder array storing target sub-addresses. Exponential Technology, Stuart T Auvinen, March 4, 1997: US05608886 (57 worldwide citation)

A target finder array in the instruction cache contains a lower portion of the target address and a block encoding indicating if the target address is within the same 2K-byte block that the branch instruction is in, or if the target address is in the next or previous 2K-byte block. The upper portion ...


8
David E Richter, Earl T Cohen, James S Blomgren: Emulation of segment bounds checking using paging with sub-page validity. Exponential Technology, Stuart T Auvinen, August 8, 1995: US05440710 (55 worldwide citation)

Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment base can be added when the virtual address is being generated. Segment bounds checking is achieved by ext ...


9
Thomas M McWilliams, Earl T Cohen, James M Bodwin, Ulrich Bruening: System including a fine-grained memory and a less-fine-grained memory. Schooner Information Technology, SNR Denton US, July 5, 2011: US07975109 (48 worldwide citation)

A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. So ...


10
Jeffrey M Broughton, Liang T Chen, William kwei cheung Lam, Derek E Pappas, Ihao Chen, Thomas M McWilliams, Ankur Narang, Jeffrey B Rubin, Earl T Cohen, Michael W Parkin, Ashley N Saulsbury, Michael S Ball: Method and apparatus for simulation system compiler. Sun Microsystems, Osha Liang, July 18, 2006: US07080365 (47 worldwide citation)

A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an ex ...