1
David B Fite, John E Murray, Dwight P Manley, Michael M McKeon, Elaine H Fite, Ronald M Salett, Tryggve Fossum: Branch prediction. Digital Equipment Corporation, Arnold White & Durkee, August 25, 1992: US05142634 (188 worldwide citation)

A branch prediction is made by searching a cache memory for branch history information associated with a branch instruction. If associated information is not found in the cache, then the branch is predicted based on a predetermined branch bias for the branch instruction's opcode; otherwise, the bran ...


2
Tryggve Fossum, Ricky C Hetherington, David B Fite Jr, Dwight P Manley, Francis X McKeen, John E Murray: Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements. Digital Equipment Corporation, Arnold White & Durkee, December 19, 1989: US04888679 (95 worldwide citation)

A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containing an element of the vector to be loaded from ...


3
David A Webb Jr, Ricky C Hetherington, John E Murray, Tryggve Fossum, Dwight P Manley: Method and apparatus for ordering and queueing multiple memory requests. Digital Equipment Corporation, Arnold White & Durkee, June 22, 1993: US05222223 (81 worldwide citation)

In a pipelined computer system 10, memory access functions (requests) are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the inst ...


4
David A Webb Jr, David B Fite, Ricky C Hetherington, Francis X McKeen, Mark A Firstenberg, John E Murray, Dwight P Manley, Ronald M Salett, Tryggve Fossum: System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer. Digital Equipment Corporation, Arnold White & Durkee, January 15, 1991: US04985825 (77 worldwide citation)

A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access ...


5
David B Fite, Ricky C Hetherington, Michael M McKeon, Dwight P Manley, John E Murray: Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer. Digital Equipment Corporation, Arnold White & Durkee, May 12, 1992: US05113515 (52 worldwide citation)

An instruction buffer of a high speed digital computer controls the flow of instruction stream to an instruction decoder. The buffer provides the decoder with nine bytes of sequential instruction stream. The instruction set used by the computer is of the variable length type, such that the decoder c ...


6
Tryggve Fossum, Dwight P Manley, Francis X McKeen, Michael M Tahranian: Memory device for storing vector registers. Digital Equipment Corporation, Finnegan Henderson Farabow Garrett and Dunner, December 1, 1992: US05168573 (35 worldwide citation)

A vector register provides the capability for simultaneously writing through at least two write ports and simultaneous reading from at least two read ports. In addition, a barber pole technique for storing words from logical vector registers into banks is provided to minimize conflicts.


7
Ricky C Hetherington, David A Webb Jr, David B Fite, John E Murray, Tryggve Fossum, Dwight P Manley: System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation. Digital Equipment Corporation, Richard J Paciulan, Denis G Maloney, September 20, 1994: US05349651 (31 worldwide citation)

In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different prog ...


8
Tryggve Fossum, Dwight P Manley, Francis X McKeen, Michael M Tehranian: Vector register system for executing plural read/write commands concurrently and independently routing data to plural read/write ports. Digital Equipment, Finnegan Henderson Farabow Garrett and Dunner, December 25, 1990: US04980817 (31 worldwide citation)

A vector register provides the capability for simultaneously writing through at least two write ports and simultaneously reading from at least two read ports. In addition, a barber pole technique for storing words from logical vector registers into banks is provided to minimize conflicts.


9
John E Murray, Mark A Firstenberg, David B Fite, Michael M McKeon, Wiliam R Grundmann, David A Webb Jr, Ronald M Salett, Tryggve Fossum, Dwight P Manley, Ricky C Hetherington: System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register. Digital Equipment Corporation, Arnold White & Durkee, August 25, 1992: US05142631 (25 worldwide citation)

A method is provided for preprocessing multiple instructions prior to execution of such instructions in a digital computer having an instruction decoder, an instruction execution unit, and multiple general purpose registers which are read to produce memory addresses during the preprocessing. The met ...


10
David A Webb Jr, Ricky C Hetherington, Ronald M Salett, Trvggve Fossum, Dwight P Manley: Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width. Digital Equipment Corporation, Arnold White & Durkee, May 28, 1991: US05019965 (20 worldwide citation)

In a computer system, the flow of data from the execution unit to the cache 28 is enhanced by pairing individual, sequential longword write operations into a simultaneous quadword write operation. Primary and secondary writebuffers 50, 52 sequentially receive the individual longwords during first an ...