1
Xavier Baie
Bruce B Doris, Dureseti Chidambarrao, Xavier Baie, Jack A Mandelman, Devendra K Sadana, Dominic J Schepis: SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device. International Business Machines Corporation, Jay H Anderson, Whitham Curtis & Christofferson P C, April 6, 2004: US06717216 (146 worldwide citation)

Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET devices, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in ...


2
Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, Jay H Anderson, Eugene I Shkurko, November 30, 2004: US06825529 (141 worldwide citation)

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


3
Xavier Baie
Bruce B Doris, Dureseti Chidambarrao, Xavier Baie, Jack A Mandelman, Devendra K Sadana, Dominic J Schepis: Field effect transistor with stressed channel and method for making same. International Business Machines Corporation, Whitham Curtis & Christofferson P C, Jay H Anderson, April 26, 2005: US06884667 (18 worldwide citation)

Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET device, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in ...


4
Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, H Daniel Schnurmann, May 20, 2008: US07374987 (16 worldwide citation)

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


5
Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, Dept 18g, February 24, 2005: US20050040460-A1

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


6
Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, International Business Machines Corporation, Dept 18g, June 17, 2004: US20040113217-A1

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


7
Michael P Belyansky, Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Oleg Gluschenkov: Structure and method to improve channel mobility by gate electrode stress modification. International Business Machines Corporation, Whitham Curtis & Christofferson P C, Ira D Blecker, December 20, 2005: US06977194 (153 worldwide citation)

In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdS ...


8
Huajie Chen, Dureseti Chidambarrao, Oleg G Gluschenkov, An L Steegen, Haining S Yang: Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions. International Business Machines Corporation, Daryl K Neff, H Daniel Schnurmann, May 10, 2005: US06891192 (102 worldwide citation)

A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain ...


9
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman: Isolation structures for imposing stress patterns. International Business Machines Corporation, Jay H Anderson, Eugene Shkurko, December 13, 2005: US06974981 (95 worldwide citation)

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate area ...


10
Dureseti Chidambarrao, Omer H Dokumaci, Oleg G Gluschenkov: Strained finFETs and method of manufacture. International Business Machines Corporation, Joseph P Abate Esq, Greenblum & Bernstein, April 3, 2007: US07198995 (91 worldwide citation)

A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material form a first island and seco ...



Click the thumbnails below to visualize the patent trend.