1
Eric T King, Michael H Perrott, Douglas F Pastorello: Offset correction and slicing level adjustment for amplifier circuits. Silicon Laboratories, Zagorin O&apos Brien & Graham, December 2, 2003: US06657488 (35 worldwide citation)

A slice and offset circuit is provided that uses a digital integrator in the feedback loop of the offset cancellation circuitry. A slice circuit receives an indication of a desired slice voltage and supplies a signal to specify the slice level, which is combined with a sensed offset level of the amp ...


2
Douglas F Pastorello, Michael H Perrott: Auto-detection between referenceless and reference clock mode of operation. Silicon Laboratories, Zagorin O&apos Brien & Graham, December 14, 2004: US06831523 (21 worldwide citation)

An internal frequency reference, such as a VCO used in a PLL, having a free-running frequency fairly well controlled within a predictable range, is used to determine which of two possible modes of operation, a referenceless or reference clock mode of operation, is used based on a detected frequency ...


3
Eric T King, Douglas F Pastorello, Bruce P Del Signore, Victor Aguilar, Frank Den Breejen, William F Gardei: Single phase bi-directional electrical measurement systems and methods using ADCs. Cirrus Logic, Steven Lin Esq, July 9, 2002: US06417792 (17 worldwide citation)

An analog to digital converter system includes first and second delta sigma converters, a calculation engine, and a serial interface on a single chip. The calculation engine is configured to calculate energy, power, rms current and voltage for single phase


4
Lizhong Sun, Bruce Del Signore, Axel Thomsen, Douglas F Pastorello: Programmable frequency divider. Silicon Laboratories, Zagorin O Brien Graham, September 26, 2006: US07113009 (14 worldwide citation)

A divider is disclosed herein. The divider includes a sequence of divide stages programmably coupled to provide a variety of divide ratios. The divider also includes one or more multiplexers to feedback the output of a divide stage to the input of a divide stage earlier in the sequence of divide sta ...


5
Douglas F Pastorello: Reduced power FIR filter. Crystal Semiconductor Corporation, Richard D Egan, J P Violette, July 13, 1999: US05923273 (12 worldwide citation)

A reduced power FIR filter may be utilized as the digital decimation filter for a delta sigma ADC. The FIR filter utilizes a serial bit stream which is part of the control path of the filter. Thus, operations of the circuitry which comprises the filter may be controlled depending upon the data prese ...


6
Joe White, Jerome Johnston, Douglas F Pastorello: Single wire interface for an analog to digital converter. Cirrus Logic, Robert P Bell, Steven Lin, Dan Shifrin, November 26, 2002: US06487674 (10 worldwide citation)

A data clock pin SCLK may be used to receive an SCLK signal as well as sleep and reset signals. During normal operation, the SCLK input pin may receive the SCLK signal, a square wave type clock signal. However, the SCLK signal may also be coupled to a one-shot within the device. When signal SCLK is ...


7
Douglas F Pastorello, Douglas Holberg, William Gene Durbin, Biranchinath Sahu, Golam R Chowdhury: Microcontroller unit (MCU) with power saving mode. Silicon Laboratories, Polansky & Associates P L L C, R Michael Reed, August 30, 2011: US08010819 (9 worldwide citation)

A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a seco ...


8
Biranchinath Sahu, Douglas F Pastorello, Golam R Chowdhury: Programmable I/O cell capable of holding its state in power-down mode. Silicon Laboratories, Howison & Arnott L, May 13, 2008: US07373533 (7 worldwide citation)

The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to th ...


9
Lizhong Sun, Douglas F Pastorello, Richard J Juhn, Axel Thomsen: Phase selectable divider circuit. Silicon Laboratories, Zagorin O Brien Graham, March 6, 2007: US07187216 (6 worldwide citation)

A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is sum ...


10
Akhil K Garlapati, Lizhong Sun, Douglas F Pastorello: High-speed divider with reduced power consumption. Silicon Laboratories, Zagorin O Brien Graham, June 23, 2009: US07551009 (5 worldwide citation)

A method for dividing a signal having a first frequency by a divide ratio includes selecting, based on the divide ratio, a first pulse width of at least one signal having a second frequency and being generated by at least a corresponding one of a plurality of pulse-width control circuits responsive ...