1
Gary Lee Boggs, Robert Samuel Cooper, Gene Robert Erickson, Douglas Edward Hundley, Gregory H Milby, P Keith Muller, Curtis Hall Stehley, Donald G Tipon: ATM/SONET network enhanced as a universal computer system interconnect. NCR Corporation, Gates & Cooper, September 28, 1999: US05959994 (82 worldwide citation)

An enhanced ATM switch with CPU node interconnect functionality and peripheral interconnect functionality and network functionality. The ATM switch provides low latency transfer between computer nodes and performs input/output operations with peripherals through the ATM network. SCSI Fibre Channel p ...


2
Douglas Edward Hundley: Devices for performing multiple independent hardware acceleration operations and methods for performing same. Tarari, Knobbe Martens Olson & Bear, September 30, 2008: US07430652 (25 worldwide citation)

Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple ind ...


3
Douglas Edward Hundley: Hardware device comprising multiple accelerators for performing multiple independent hardware acceleration operations. LSI Corporation, April 12, 2011: US07925863 (3 worldwide citation)

Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple ind ...


4
Douglas Edward Hundley: Method and apparatus for chaining multiple independent hardware acceleration operations. Knobbe Martens Olson & Bear, October 2, 2008: US20080244126-A1

Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple ind ...


5
Douglas Edward Hundley: Method and apparatus for chaining multiple independent hardware acceleration operations. Knobbe Martens Olson & Bear, December 15, 2005: US20050278502-A1

Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple ind ...