1
William C Madden, Douglas E Sanders, G Michael Uhler, William R Wheeler: Application of state silos for recovery from memory management exceptions. Digital Equipment Corporation, Arnold White & Durkee, June 2, 1992: US05119483 (47 worldwide citation)

To reduce the processing time required for correcting a fault, the instruction decorder segment and the first execution segment of a pipelined processor are provided with "state silos" that are operative during normal instruction execution to save a sufficient amount of state information to immediat ...


2
Douglas E Sanders, Michael A Callander: Two-level protocol for multi-component bus ownership, and implementation in a multi-processor cache write back protocol. Digital Equipment Corporation, Denis G Maloney, Barry Young, Ronald Myrick, March 9, 1993: US05193163 (47 worldwide citation)

A method and apparatus for monitoring transactions on a system bus for invalidate requests, including a queue for storing the invalidate requests which is divided into two parts. The first part of the queue is contained within a cache controller to ensure that an invalidate request is immediately av ...


3
Michael A Callander, Douglas E Sanders: Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions. Digital Equipment Corporation, Albert P Cefalo, A Sidney Johnston, James F Thompson, January 4, 1994: US05276852 (35 worldwide citation)

A CPU module has a processor, cache memory, cache controller, and system interface attached to a processor bus. The system interface is attached to a system bus shared by memory, I/O, and other CPU modules. The cache controller requests control of the processor bus from the processor, and grants con ...


4
Douglas E Sanders, George M Uhler, John F Brown III: Pipelined digital CPU with deadlock resolution. Digital Equipment Corporation, Arnold White & Durkee, April 9, 1991: US05006980 (32 worldwide citation)

A pipelined CPU employs separate microinstruction pipelines for the execution unit and memory management unit. Deadlocks can occur in a pipelined CPU when there is data dependency in two consecutive instructions. The later instruction may stall the pipeline if operands fetched by an earlier instruct ...


5
Michael A Callander, Linda Chao, Douglas E Sanders: Apparatus for suppressing an error report from an address for which an error has already been reported. Digital Equipment Corporation, Barry N Young, Ronald C Hudgens, July 6, 1993: US05226150 (28 worldwide citation)

A write-back cache memory system is disclosed which includes a source of a sequence of memory addresses and a tag store coupled to the source of addresses and accessed by an index portion of said addresses, which produces information relating to the addresses. The write-back cache memory system also ...


6
Charles M Sanders, Douglas E Sanders Sr: Lawn mower starting aid. Norman B Rainer, October 19, 1993: US05253540 (9 worldwide citation)

A device for pulling the starter cord of a lawn mower engine utilizes a pulling cable disposed about upper and lower pulleys on a vertical post. The upper extremity of the pulling cable is attached to a lever pivotally joined to the vertical post. Downward movement of the lever causes the starter co ...


7
Soha M N Hassoun, Douglas E Sanders: Method and apparatus for parity generation. Digital Equipment Corporation, Arthur W Fisher, Denis G Maloney, Lindsay McGuinness, September 17, 1996: US05557622 (6 worldwide citation)

A parity generator for multibit binary data in which only a subset of bits change at one time includes a circuit for determining whether the number of bits in the subset to be changed is odd or even. A toggle signal generator generates a toggle signal only if the number of bits to be changed is odd. ...


8
Charles M Sanders, Douglas E Sanders Sr: Lawn mower starting device. Norman B Rainer, February 15, 1994: US05285693 (5 worldwide citation)

A device for pulling the starter cord of a lawn mower engine utilizes a pulling cable attached to a pulley wheel activated by a high torque electric motor. An elongated base supports an upright post, upon which the motor is mounted. A chute protectively guides the cable as it spans the distance betw ...


9
James W Keeley, Douglas E Sanders, Andrew Hyonil Chong: Bridge apparatus and methods for coupling multiple non-fibre channel devices to a fibre channel arbitrated loop. LSI Corporation, Duft Bornsen & Fishman, February 14, 2012: US08116330 (1 worldwide citation)

Apparatus and methods for an enhanced bridge device for coupling multiple non-Fiber Channel storage devices to a Fiber Channel Arbitrated Loop (FC-AL) communication medium. Features and aspects hereof provide for FC-AL enhanced circuits for processing loop port bypass (LPB) and loop port enable (LPE ...


10
James W Keeley, Douglas E Sanders, Daniel W Meyer, Andrew Hyonil Chong, Ju Ching Tang: Apparatus and methods for access fairness for a multiple target bridge/router in a fibre channel arbitrated loop system. LSI Corporation, Duft Bornsen & Fettig, February 19, 2013: US08379665

Apparatus and methods improved fair access to a Fiber Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC ...