1
George H Bean, Terry L Borden, Mark S Farrell, Peter H Gum, Roger E Hough, Francis E Johnson, Donald W McCauley, Mark E Rakhmilevich, John C Rathjen, Casper A Scalzi, John F Scanlon, Leslie W Wyman: Logical resource partitioning of a data processing system. International Business Machines Corporation, Bernard M Goldman, June 27, 1989: US04843541 (299 worldwide citation)

The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest pr ...


2
Clifford O Hayden, Robert J Hurban, Donald W McCauley, John S Murdock Jr, Susan B Stillman: Type 1, 2 and 3 retry and checkpointing. International Business Machines Corporation, Lynn L Augspurger, Richard M Ludwin, December 7, 1993: US05269017 (71 worldwide citation)

An improved error recovery system in which all operations which the Central Processor performs are categorized into one of a plurality of recovery types. The determination of category is made based on which architected and machine dependent facilities they manipulate and the manner in which the faci ...


3
Norman C Chou, Peter H Gum, Roger E Hough, Moon J Kim, James C Mazurowski, Donald W McCauley, Casper A Scalzi, John F Scanlon, Leslie W Wyman: CPU expansive gradation of I/O interruption subclass recognition. International Business Machines Corporation, Bernard M Goldman, June 22, 1993: US05222215 (51 worldwide citation)

A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlle ...


4
Bryan Black, Murali M Annavaram, Donald W McCauley, John P Devale: Prefetching from dynamic random access memory to a static random access memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 4, 2011: US08032711 (37 worldwide citation)

Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch l ...


5
Benjamin C Serebrin, Donald W McCauley: Guest interrupt controllers for each processor to aid interrupt virtualization. Advanced Micro Devices, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, November 8, 2011: US08055827 (18 worldwide citation)

In one embodiment, a system comprises a processor, a first interrupt controller coupled to the processor, and a second interrupt controller coupled to the processor. The first interrupt controller is configured to signal the processor for an interrupt in response to receiving a first interrupt messa ...


6
Ronald F Hill, Donald W McCauley, Stephen J Nadas, James R Robinson: Method and system for controlling references to system storage by overriding values. International Business Machines Corporation, Lynn L Augspurger Esq Heslin & Rothenberg P C, March 25, 1997: US05615354 (12 worldwide citation)

A method and system for controlling references to system storage. Milli-code mode provides a flexible technique for overriding storage controls associated with referencing system storage of a data processing system. The storage controls to be overridden are not replaced and therefore, a restore of t ...


7
Hemant G Rotithor, Randy B Osborne, Donald W McCauley: High performance memory device-state aware chipset prefetcher. Intel Corporation, Pillsbury Winthrop Shaw Pittman, January 3, 2006: US06983356 (8 worldwide citation)

A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the memory bandwidth utilization (MBU) rate is above a MBU threshold level and the prefetch buffer hit rate (PBHR ...


8
Donald W McCauley, Richard J Schmalz, Ronald M Smith Sr, Susan B Stillman: Execution of page data transfer by PT processors and issuing of split start and test instructions by CPUs coordinated by queued tokens. International Business Machines Corporation, Bernard M Goldman, January 31, 1995: US05386560 (4 worldwide citation)

Asynchronously transfers blocks of data (called pages) between two different electronic media of a data processing system. The different media may be a system main storage and a system expanded storage or a non-volatile external type of storage, either of which use different addressing than the main ...


9
Mohammed H Taufique, Derwin Jallice, Donald W McCauley, John P DeVale, Edward A Brekelbaum, Jeffrey P Rupley II, Gabriel H Loh, Bryan Black: Memory array on more than one die. Intel Corporation, Matthew C Fagan, April 6, 2010: US07692946 (3 worldwide citation)

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital sign ...


10
Mohammed H Taufique, Derwin Jallice, Donald W McCauley, John P DeVale, Edward A Brekelbaum, Jeffrey P Rupley II, Gabriel H Loh, Bryan Black: Memory array on more than one die. Intel Corporation, Guojun Zhou, November 15, 2011: US08059441 (2 worldwide citation)

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital sign ...