1
Donald L Wollesen: High conductivity interconnection line. Advanced Micro Devices, Lowe Price LeBlanc & Becker, August 19, 1997: US05659201 (193 worldwide citation)

High conductivity interconnection lines are formed of high conductivity material, such as copper, employing barrier layers impervious to the diffusion of copper atoms. Higher operating speeds are obtained with conductive interconnection lines, preferably copper interconnection lines, formed above th ...


2
Yowjuang W Liu, Donald L Wollesen: Trench-gated vertical combination JFET and MOSFET devices. Advanced Micro Devices, Foley & Lardner, December 19, 2000: US06163052 (119 worldwide citation)

A combination vertical MOSFET and JFET device (18,22) is formed in a mesa (20,24) of semiconductor material. A top gate (44,68) of the device is formed by creating a preferably annular trench (36,58) that extends downwardly from the surface of the semiconductor layer, creating a thin gate insulator ...


3
Donald L Wollesen, Homi Fatemi: Short channel self-aligned VMOS field effect transistor. Advanced Micro Devices, Foley & Larnder, September 28, 1999: US05960271 (77 worldwide citation)

A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls ...


4
Donald L Wollesen: Low capacitance interconnection. Advanced Micro Devices, May 4, 1999: US05900668 (61 worldwide citation)

A semiconductor device having reduced parasitic capacitance and, consequentially increased integrated circuit speed, is achieved by removing sections of dielectric interlayers which do not support conductive patterns, as by anisotropic etching, to form air gaps which can remain or are filled in with ...


5
Donald L Wollesen: Silicon-on-insulator configuration which is compatible with bulk CMOS architecture. Advanced Micro Devices, Lariviere Grubman & Payne, April 10, 2001: US06215155 (48 worldwide citation)

A method for creating a SOI CMOS type device compatible with bulk CMOS using a bulk CMOS physical layout data base. The method uses the P-well and N-well masks used in fabrication of bulk CMOS devices. The N-well and P-well regions are fabricated by implanting the appropriate dopants above and below ...


6
Donald L Wollesen: Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask. Advanced Micro Devices, John P Taylor, May 14, 1991: US05015595 (46 worldwide citation)

A method for making an integrated circuit structure having both PMOS and NMOS devices with lightly doped (LDD) source and drain regions is disclosed utilizing a single photoresist mask in which a substrate is implanted with a low concentration dopant of a first conductivity type through a silicon ni ...


7
Donald L Wollesen: Thin oxide anti-fuse. Advanced Micro Devices, February 4, 2003: US06515344 (40 worldwide citation)

A programmable anti-fuse is formed simultaneously with transistors and other devices on a semiconductor substrate. Embodiments include an anti-fuse comprising a doped active region in the substrate, such as an n+ region, a gate oxide layer, and a gate, such as polysilicon, of a minimum size acc ...


8
Donald L Wollesen, William Meuli, Philip S Shiota: CMOS P-Well selective implant method. American Microsystems, Skjerven Morrill Jensen MacPherson & Drucker, December 22, 1981: US04306916 (36 worldwide citation)

A method for fabricating a complementary metal-oxide-silicon (CMOS) integrated circuit device by forming a composite layer of oxide and nitride on the surface of a silicon substrate defined into predetermined areas for the subsequent formation of transistors, masking the substrate to expose preselec ...


9
Nguyen Duc Bui, Donald L Wollesen: Reduced electromigration interconnection line. Advanced Micro Devices, Lowe Price LeBlanc & Becker, January 27, 1998: US05712510 (35 worldwide citation)

The electromigration lifetime of a metal interconnection line is increased by adjusting the length of the interconnection line, or providing longitudinally spaced apart holes or vias, to optimize the Backflow Potential Capacity of the metal interconnection line.


10
Donald L Wollesen: Low capacitance interconnection. Advanced Micro Devices, November 14, 2000: US06146985 (34 worldwide citation)

A semiconductor device having reduced parasitic capacitance and, consequentially increased integrated circuit speed, is achieved by removing sections of dielectric interlayers which do not support conductive patterns, as by anisotropic etching, to form air gaps which can remain or are filled in with ...



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