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Gilbert Wolrich, Debra Bernstein, Donald Hooper, Matthew J Adiletta, William Wheeler: Thread signaling in multi-threaded network processor. Intel Corporation, Fish & Richardson P C, September 23, 2003: US06625654 (120 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory cont ...


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Gilbert Wolrich, Debra Bernstein, Donald Hooper, Matthew J Adiletta, William Wheeler: Thread signaling in multi-threaded processor. Intel Corporation, Fish & Richardson P C, September 19, 2006: US07111296 (33 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory cont ...


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Gilbert Wolrich, Matthew I Adiletta, William Wheeler, Debra Bernstein, Donald Hooper: Double shift instruction for micro engine used in multithreaded parallel processor architecture. Intel Corporation, Fish & Richardson P C, March 13, 2007: US07191309 (6 worldwide citation)

A method of operating a processor includes concatenating a first word and a second word to produce an intermediate result, shifting the intermediate result by a specified shift amount and storing the shifted intermediate result in a third word, to create an address.


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Gilbert Wolrich, Debra Bernstein, Donald Hooper, Matthew J Adiletta, William Wheeler: Thread signaling in multi-threaded network processor. Intel Corporation a California Corporation, Fish & Richardson PC, May 20, 2004: US20040098496-A1

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory cont ...


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Suresh Kalkunte, Hugh Wilkinson, Gilbert Wolrich, Mark Rosenbluth, Donald Hooper: Traffic management. Blakely Sokoloff Taylor & Zafman, January 27, 2005: US20050018601-A1

In general, in one aspect, the disclosure describes a system to process packets received over a network. The system includes a receive process of at least one thread of a network processor to receive data of packets belonging to different flows. The system also includes a transmit process of at leas ...


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Prashant R Chandra, Uday Naik, Alok Kumar, Ameya Varde, Donald Hooper, Debra Bernstein, Myles J Wilde, Mark Rosenbluth: Method and apparatus for meeting a given content throughput using at least one memory channel. Blakely Sokoloff Taylor & Zafman, September 8, 2005: US20050198361-A1

A method and apparatus for meeting a given content throughput using at least one memory channel is generally described. In accordance with one example embodiment of the invention, a method to meet a given content throughput using at least one memory channel comprising, comparing the size of at least ...


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