1
Gurbir Singh, Robert J Greiner, Stephen S Pawlowski, David L Hill, Donald D Parker: Quad pumped bus architecture and protocol. Intel Corporation, Antonelli Terry Stout & Kraus, July 29, 2003: US06601121 (63 worldwide citation)

A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of th ...


2
Donald D Parker, Darrell D Boggs, Alan B Kyker: Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 21, 2000: US06041403 (49 worldwide citation)

A method and apparatus for decoding a macroinstruction, the macroinstruction including an operational code (opcode) and a specification of an operand, is described. The method includes two primary steps, which are performed either serially or in parallel. When performed serially, the steps may be pe ...


3
Adrian L Carbine, Gary L Brown, Donald D Parker: Decoder for decoding multiple instructions in parallel. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 13, 1997: US05630083 (45 worldwide citation)

A decoder for decoding multiple instructions in parallel, including a full decoder that can decode an instruction into multiple micro-operations, and a partial decoder that can decode a subset of the full instruction set.


4
Darrell D Boggs, Gary L Brown, Michael M Hancock, Donald D Parker, Gail M Rupnick: Method for state recovery during assist and restart in a decoder having an alias mechanism. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 15, 1996: US05566298 (39 worldwide citation)

A state recovery and restart method that simplifies assist handling. The recovery and restart method also handles micro-branch mispredictions. An assist sequence is executed in microcode to assist an error-causing macroinstruction. If data is required from an error-causing macroinstruction, it is fe ...


5
Gary L Brown, Donald D Parker: Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 4, 1997: US05600806 (34 worldwide citation)

A circuit and method for supplying and aligning a block of multiple variable length macro instructions to an instruction buffer. Only one cycle is required to align and rotate the block of instruction code. A last byte vector of the instruction code in the instruction buffer is scanned from the last ...


6
Gary L Brown, Adrian L Carbine, Donald D Parker: Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 30, 1997: US05673427 (32 worldwide citation)

A micro-operation queue for holding a plurality of micro-operations supplied simultaneously by a decoder. A plurality of packing multiplexers are coupled to receive the plurality of micro-operations, and valid bits associated therewith, and to provide packed micro-operation data output in which the ...


7
Gary L Brown, Donald D Parker: Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 17, 1996: US05586277 (30 worldwide citation)

A circuit and method for simultaneously steering multiple aligned macroinstructions from an instruction buffer to a decoder that receives and decodes multiple macroinstructions in parallel. A first macroinstruction is supplied to a first decoder by steering a first predetermined number of bytes foll ...


8
Gurbir Singh, Robert J Greiner, Stephen S Pawlowski, David L Hill, Donald D Parker: Quad pumped bus architecture and protocol. Intel Corporation, Antonelli Terry Stout & Kraus, August 19, 2003: US06609171 (16 worldwide citation)

A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of th ...


9
Darrell D Boggs, Gary L Brown, Michael M Hancock, Donald D Parker: Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 24, 1996: US05559974 (15 worldwide citation)

A decoder that includes a micro-alias register to store information from a micro-operation for use by later micro-operations in the micro-operation flow. The decoder includes one or more XLAT PLAs that produces PLA control micro-operations ("Cuops"), a microcode sequencing unit that produces microco ...


10
Gary L Brown, Donald D Parker: Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 13, 1998: US05822555 (15 worldwide citation)

A circuit and method for supplying and aligning a block of multiple variable length macro instructions to an instruction buffer. Only one cycle is required to align and rotate the block of instruction code. A last byte vector of the instruction code in the instruction buffer is scanned from the last ...