1
Jared LeVan Zerbe, Kevin S Donnelly, Stefanos Sidiropoulos, Donald C Stark, Mark A Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W Garlepp, Tsyr Chyang Ho, Benedict Chung Kwong Lau: Bus system optimization. Rambus, Pennie & Edmonds, November 4, 2003: US06643787 (243 worldwide citation)

A bus system comprising a master connected to one or more slave devices via a bus is disclosed. The bus system is able to effectively communicate control information during a calibration phase and to individually determine appropriate timing and/or voltage offsets for each slave device. The offsets ...


2
Kevin S Donnelly, Pak Shing Chau, Mark A Horowitz, Thomas H Lee, Mark G Johnson, Benedict C Lau, Leung Yu, Bruno W Garlepp, Yiu Fai Chan, Jun Kim, Chanh Vi Tran, Donald C Stark: Delay-locked loop circuitry for clock delay adjustment. Rambus, Pennie & Edmonds, September 26, 2000: US06125157 (201 worldwide citation)

Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each s ...


3
Richard E Perego, Donald C Stark, Frederick A Ware: Memory device supporting a dynamically configurable core organization. Rambus, Silicon Edge Law Group, Arthur J Behiel, May 3, 2005: US06889304 (167 worldwide citation)

Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow m ...


4
Tohru Furuyama, Donald C Stark: Semiconductor memory with bypass circuit. Kabushiki Kaisha Toshiba, Banner & Allegretti, December 26, 1995: US05479370 (166 worldwide citation)

A semiconductor memory of this invention comprises a memory cell array containing memory cells arranged in matrix form, word lines each connected to all the memory cells in the same row, and bit lines each connected to all the memory cells in the same column, a shift register containing a plurality ...


5
Kevin S Donnelly, Pak Shing Chau, Mark A Horowitz, Thomas H Lee, Mark G Johnson, Benedict C Lau, Leung Yu, Bruno W Garlepp, Yiu Fai Chan, Jun Kim, Chanh Vi Tran, Donald C Stark, Nhat M Nguyen: Delay locked loop circuitry for clock delay adjustment. Rambus, Pennie & Edmonds, March 25, 2003: US06539072 (141 worldwide citation)

Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit del ...


6
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen, Thomas J Holman, Andrew V Anderson, Peter D MacWilliams: High performance cost optimized memory with delayed memory writes. Rambus Incorporated, Intel Corporation, Pennie & Edmonds, June 13, 2000: US06075730 (134 worldwide citation)

A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core wr ...


7
Ely K Tsern, Richard M Barth, Craig E Hampel, Donald C Stark: Power control system for synchronous memory device. Rambus, Gary S Williams, Pennie & Edmonds, March 2, 2004: US06701446 (117 worldwide citation)

A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the m ...


8
Jared LeVan Zerbe, Kevin S Donnelly, Stefanos Sidiropoulos, Donald C Stark, Mark A Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W Garlepp, Tsyr Chyang Ho, Benedict Chung Kwong Lau: Integrated circuit with timing adjustment mechanism and method. Rambus, Morgan Lewis & Bockius, September 27, 2005: US06950956 (115 worldwide citation)

An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock cir ...


9
Ely K Tsern, Thomas J Holman, Richard M Barth, Andrew V Anderson, Paul G Davis, Craig E Hampel, Donald C Stark, Abhijit M Abhyankar: Memory device and system including a low power interface. Intel Corporation, Rambus, Pennie & Edmonds, April 23, 2002: US06378018 (113 worldwide citation)

A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power inte ...


10
Donald C Stark: Single-clock, strobeless signaling system. Rambus, November 11, 2003: US06646953 (105 worldwide citation)

A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied ...