1
Thomas B Brightman, Andrew T Brown, John F Brown, James A Farrell, Andrew D Funk, David J Husak, Edward J McLellan, Mark A Sankey, Paul Schmitt, Donald A Priore: Digital communications processor. Freescale Semiconductor, Gordon E Nelson, August 29, 2006: US07100020 (52 worldwide citation)

An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). T ...


2
Dilip K Bhavsar, Donald A Priore: Embedded RAM with self-test and self-repair with spare rows and columns. Compaq Information Technologies Group, Hamilton Brook Smith & Reynolds P C, June 18, 2002: US06408401 (48 worldwide citation)

A self-repair method for a random access memory (RAM) array comprises writing a value to the memory array, reading a value from the memory array and comparing the read and write values to identify faulty memory cells in the memory array. An address of a newly-discovered faulty memory cell is compare ...


3
William J Dally, John Edmondson, Donald A Priore, Ephrem Wu, John W Poulton: Architectures for a single-stage grooming switch. LSI Logic Corporation, Hamilton Brook Smith & Reynolds P C, October 19, 2004: US06807186 (8 worldwide citation)

A single-stage grooming switch is provided for switching streams of multiplexed traffic, such as SONET STS-48, in both time and space domains. In particular, the switch implements a distributed demultiplexing architecture for switching between any input timeslot to any output timeslot at a reduced l ...


4
Thomas B Brightman, Andrew D Funk, David J Husak, Edward J McLellan, Andrew T Brown, John F Brown, James A Farrell, Donald A Priore, Mark A Sankey, Paul Schmitt: High speed and high throughput digital communications processor with efficient cooperation between programmable processing components. Freescale Semiconductor, Gordon E Nelson, January 12, 2010: US07647472 (5 worldwide citation)

An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). T ...


5
Donald A Priore, Dilip K Bhavsar, Tina P Zou: Encoding of failing bit addresses to facilitate multi-bit failure detect using a wired-OR scheme. Digital Equipment Corporation, Hamilton Brook Smith & Reynolds P C, June 13, 2000: US06076176 (4 worldwide citation)

A technique for encoding failing bit addresses in a memory array with redundant portions such as column slices. The address or other identification of a column slice or other portion of a memory array is identified to test logic using a wired-OR bus configuration. The technique assigns a code consis ...


6
Russell Schreiber, Keith Kasprak, Donald A Priore: Bitcell simulation device and methods. Advanced Micro Devices, April 26, 2011: US07933760 (2 worldwide citation)

A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each norm ...


7
Mike Butler, Donald A Priore, Steven Beigelmacher: Odd and even start bit vectors. Advanced Micro Devices, Volpe and Koenig P C, November 19, 2013: US08589661

A method and apparatus are presented for processing a stream of information, including preprocessing the stream, which includes partitioning the stream into packets of interest; determining boundaries for the packets of interest, wherein a packet boundary is either a start location or an end locatio ...


8
Kevin M Gillespie, Timothy J Correia, Donald A Priore: Method for analyzing sensitivity and failure probability of a circuit. Advanced Micro Devices, Volpe and Koenig P C, February 18, 2014: US08656339

A method, implemented in a processor, of determining a likelihood of failure of a circuit to be made in accordance with a circuit design, and a computer-readable storage medium storing instructions to the processor for carrying out the method. A sensitivity of a figure of merit to each variable of a ...


9
Donald A Priore, John G Petrovick Jr, Stephen V Kosonocky, Robert S Orefice: Fault detection for a distributed signal line. Advanced Micro Devices, March 29, 2016: US09300293

An integrated circuit device includes a first signal line for distributing a first signal. The first signal line includes a plurality of branch lines, and a leaf node is defined at an end of each branch line. First logic is coupled to the leaf nodes and operable to generate a first status signal ind ...


10
Thomas B Brightman, Andrew D Funk, David J Husak, Edward J McLellan, Andrew T Brown, John F Brown, James A Farrell, Donald A Priore, Mark A Sankey, Paul Schmitt: Digital communications processor. Gordon E Nelson Patent Attorney PC, December 28, 2006: US20060292292-A1

An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). T ...