1

2

3
Don A Van Dyke, Timothy J Cramer, James C Rasbold, Kelly T O Hair, David M Cox, David A Seberger, Linda J O Gara, Jon A Masamitsu, Robert E Strout II, Ashok Chandramouli: Computer with integrated hierarchical representation (IHR) of program wherein IHR file is available for debugging and optimizing during target execution. Supercomputer Systems Partnership, Patterson & Keough, December 29, 1992: US05175856 (163 worldwide citation)

A modular compilation system that utilizes a fully integrated hierarchical representation as a common intermediate representation to compile source code programs written in one or more procedural programming languages into an executable object code file. The structure of the integrated common interm ...


4
Douglas R Beard, Andrew E Phelps, Michael A Woodmansee, Richard G Blewett, Jeffrey A Lohman, Alexander A Silbey, George A Spix, Frederick J Simmons, Don A Van Dyke: Scalar/vector processor. Cray Research, Schwegman Lundberg & Woessner, July 4, 1995: US05430884 (95 worldwide citation)

The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plu ...


5
James C Rasbold, Don A Van Dyke: Method for optimizing instruction scheduling for a processor having multiple functional resources. Supercomputer Systems Partnership, Patterson & Keough, April 13, 1993: US05202975 (56 worldwide citation)

A method for scheduling instructions for a processor having multiple functional resources wherein the reordering of the instructions is accomplished in response to a simulation of the run-time environment of the target machine. The simulation of the run-time environment of the target machine is perf ...


6
Douglas R Beard, Andrew E Phelps, Michael A Woodmansee, Richard G Blewett, Jeffrey A Lohman, Alexander A Silbey, George A Spix, Frederick J Simmons, Don A Van Dyke: Method and apparatus for chaining vector instructions. Cray Research, Schwegman Lundberg Woessner & Kluth P A, June 17, 1997: US05640524 (23 worldwide citation)

A vector processing system includes a main memory, vector registers, vector resources for accessing memory to transfer vector data between main memory and the vector registers and to perform operations on the vector data. Data words stored in non-consecutive address locations of a segment of main me ...


7
Douglas R Beard, Andrew E Phelps, Michael A Woodmansee, Richard G Blewett, Jeffrey A Lohman, Alexander A Silbey, George A Spix, Frederick J Simmons, Don A Van Dyke: Vector processor having registers for control by vector resisters. Cray Research, Schwegman Lundberg Woessner & Kluth P A, August 6, 1996: US05544337 (22 worldwide citation)

The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plu ...


8
Korbin Van Dyke, Paul Campbell, Don A Van Dyke, Ali Alasti, Stephen C Purcell: Method and apparatus for dynamic allocation of processing resources. Advanced Micro Devices, Sterne Kessler Goldstein & Fox P L L C, February 9, 2010: US07661107 (19 worldwide citation)

A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with fun ...


9
James C Rasbold, Don A Van Dyke: Method for inserting a path instruction during compliation of computer programs for processors having multiple functional units. Supercomputer Systems Partnership, Schwegman Lundberg and Woessner, April 26, 1994: US05307478 (19 worldwide citation)

A method is provided for inserting a path instruction during compilation of computer programs for a processor having multiple functional resources. A path instruction is inserted in the order of object code instruction during the reordering of the instructions in response to a simulation of the run- ...


10
Douglas R Beard, Andrew E Phelps, Michael A Woodmansee, Richard G Blewett, Jeffrey A Lohman, Alexander A Silbey, George A Spix, Frederick J Simmons, Don A Van Dyke: Partitioned addressing apparatus for vector/scalar registers. Cray Research, Schwegman Lundberg Woessner & Kluth P A, April 28, 1998: US05745721 (16 worldwide citation)

A scalar/vector processor capable of concurrent scaler and vector operations includes scalar resources to process scalar instructions, and vector resources adapted to be operated concurrently with the scalar resources and with one another to process vector instructions. The scalar resources include ...