11
Deborah T Marr, Dion Rodgers: Method and apparatus for pausing execution in a processor or the like. Intel Corporation, Kenyon & Kenyon, December 30, 2003: US06671795 (26 worldwide citation)

A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET instruction and a READ instruction. When a SET flag is retrieved for a given thread, the SET instruction sets ...


12
Gilbert Neiger, Steven M Bennett, Dion Rodgers, Richard A Uhlig, Lawrence O Smith III: Transitioning between virtual machine monitor domains in a virtual machine environment. Intel Corporation, Thomas R Lane, August 25, 2009: US07581219 (24 worldwide citation)

Techniques for handling certain virtualization events occurring within a virtual machine environment. More particularly, at least one embodiment of the invention pertains to handling events related to the sub-operating system mode using a dedicated virtual machine monitor (VMM) called the system man ...


13
Gilbert Neiger, Andrew V Anderson, Steven M Bennett, Jason Brandt, Erik Cota Robles, Stalinselvaraj Jeyasingh, Alain Kägi, Sanjoy K Mondal, Rajesh Parthasarathy, Dion Rodgers, Lawrence O Smith, Richard A Uhlig: Support for nested fault in a virtual machine environment. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 4, 2007: US07305592 (20 worldwide citation)

In one embodiment, information pertaining to a first fault occurring during operation of a virtual machine (VM) is stored in a first field. A second fault is detected while delivering the first fault to the VM, and a determination is made as to whether the second fault is associated with a transitio ...


14
Andrew Glew, Scott Dion Rodgers: Method and apparatus for changing privilege levels in a computer system without use of a call gate. Intel Corporation, Laura L Mikkola, September 7, 1999: US05948097 (19 worldwide citation)

A method and apparatus for performing a system call in a system having a user privilege level and a kernel privilege level, wherein the kernel privilege level is higher than the user privilege level is disclosed. A sequence of instructions is executed at the user privilege level including a first in ...


15
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard Uhlig, Larry Smith, Dion Rodgers: Extended paging tables to map guest physical memory addresses from virtual memory page tables to host physical memory addresses in a virtual machine system. Intel Corporation, Thomas R Lane, February 8, 2011: US07886126 (16 worldwide citation)

A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a referenc ...


16
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Dion Rodgers, Richard A Uhlig, Lawrence O Smith, Barry E Huntley: Virtualization event processing in a layered virtualization architecture. Intel Corporation, Thomas R Lane, September 18, 2012: US08271978 (14 worldwide citation)

Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determin ...


17
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia: PCI express enhancements and extensions including transactions having prefetch parameters. Intel Corporation, David P McAbee, January 17, 2012: US08099523 (13 worldwide citation)

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Messa ...


18
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia: PCI express enhancements and extensions. Intel Corporation, David P McAbee, July 24, 2012: US08230120 (13 worldwide citation)

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Messa ...


19
Stavros Kalafatis, Micheal D Cranford, Scott D “Dion” Rodgers, Brinkley Sprunt: Qualification of event detection by thread ID and thread privilege level. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 4, 2008: US07448025 (13 worldwide citation)

A method and apparatus for monitoring the performance characteristics of a multithreaded processor executing instructions from two or more threads simultaneously. Event detectors detect the occurrence of specific processor events during the execution of instructions from threads of a multithreaded p ...


20
Hong Wang, Gautham N Chinya, Richard A Hankins, Shivnandan D Kaushik, Bryant Bigbee, John Shen, Per Hammarlund, Xiang Zou, Jason W Brandt, Prashant Sethi, Douglas M Carmean, Baiju V Patel, Scott Dion Rodgers, Ryan N Rakvic, John L Reid, David K Poulsen, Sanjiv M Shah, James Paul Held, James Charles Abel: Sequencer address management. Intel Corporation, David P McAbee, June 22, 2010: US07743233 (12 worldwide citation)

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses ...