1
Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu: Method and apparatus for entering and exiting multiple threads within a multithreaded processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 3, 2005: US06889319 (79 worldwide citation)

A method includes maintaining a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status for an associated thread of multiple threads being executed within a multithreaded processor. Status for a first thread is detected, responsive to which a func ...


2
Scott Dion Rodgers, Rohit Vidwans, Joel Huang, Michael A Fetterman, Kamla Huck: Method and apparatus for generating event handler vectors based on both operating mode and event type. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 30, 1999: US05889982 (77 worldwide citation)

A method and apparatus for handling events, such as those which occur in a processor. An event vector is formed by combining event type information indicating a type of event in the processor and mode information indicating an operating mode of the processor. A microcode event handler vector is gene ...


3
Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur: Method and apparatus for processing an event occurrence within a multithreaded processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 17, 2002: US06496925 (75 worldwide citation)

A method includes detecting a first event occurrence for a first thread being processed within a multithreaded processor. Responsive to the detection of this first event occurrence, a second thread being processed within the multithreaded processor is monitored to detect a clearing point for this se ...


4
Dion Rodgers, Bret Toll, Aimee Wood: Method and apparatus for disabling a clock signal within a multithreaded processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 12, 2002: US06357016 (64 worldwide citation)

A method includes maintaining an indication of a pending event with respect to each of a number of threads supported within a multithreaded processor. An indication is also maintained of an active or inactive state for each of the multiple threads. A clock disable condition is detected. This clock d ...


5
Dion Rodgers, Bret Toll, Aimee Wood: Method and apparatus for disabling a clock signal within a multithreaded processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 19, 2005: US06883107 (62 worldwide citation)

A method includes maintaining an indication of a pending event with respect to each of a number of threads supported within a multithreaded processor. An indication is also maintained of an active or inactive state for each of the multiple threads. A clock disable condition is detected. This clock d ...


6
Dion Rodgers, Deborah T Marr, David L Hill, Shiv Kaushik, James B Crossland, David A Koufaty: Method and apparatus for suspending execution of a thread until a specified memory access occurs. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 22, 2008: US07363474 (59 worldwide citation)

Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of ...


7
David L Hill, Deborah T Marr, Dion Rodgers, Shiv Kaushik, James B Crossland, David A Koufaty: Coherency techniques for suspending execution of a thread until a specified memory access occurs. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 24, 2006: US07127561 (51 worldwide citation)

Coherency techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes a cache, execution logic to execute an instruction having an operand indicating a monitor address and a bus controller. In one embodiment, the bus controller is t ...


8
Lawrence O Smith, S Dion Rodgers: Method and apparatus for processing events in a multithreaded processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 15, 2005: US06857064 (39 worldwide citation)

In a multithreaded processor, events are categorized according to which of a “soft” state clearing (“nuke”) process and a “hard” nuke process should be performed in response to each event. When an event is detected for a thread, either the soft nuke or hard nuke process is executed, according to the ...


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Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur: Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 2, 2006: US07039794 (38 worldwide citation)

A method includes detecting a first pending event related a first thread being processed within a multithreaded processor. Responsive to the detection of the first pending event, a second thread being processed within the multithreaded processor is monitored to detect an event handling point for the ...


10
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Fallk, Avi, Ilan Pardo, Eran Tamari, Ellezer Weissmann, Doron Shamia: PCI express enhancements and extensions. Intel Corporation, David P McAbee, May 24, 2011: US07949794 (32 worldwide citation)

A method and apparatus for enhancing /extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Mess ...