1
G Glenn Henry, Dinesh K Jain, Terry Parks: Microprocessor with program-accessible re-writable non-volatile state embodied in blowable fuses of the microprocessor. VIA Technologies, E Alan Davis, James W Huffman, February 16, 2010: US07663957 (29 worldwide citation)

A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is blown or unblown, in response to the ...


2
G Glenn Henry, Dinesh K Jain: Apparatus and method for override access to a secured programmable fuse array. VIA Technologies, Richard K Huffman, James W Huffman, August 14, 2012: US08242800 (26 worldwide citation)

An apparatus in an integrated circuit for re-enabling the use of precluded extended JTAG operations. The apparatus includes a JTAG control chain, a feature fuse, a machine specific register, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations ...


3
Gerard M Col, G Glenn Henry, Dinesh K Jain: Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection. IP First L L C, E Alan Davis, James W Huffman, February 13, 2001: US06189091 (20 worldwide citation)

An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A dynamic branch predictor speculatively updates global branch history information based on the prediction of a first branch instruction so that the p ...


4
G Glenn Henry, Dinesh K Jain: Apparatus and method for compression and decompression of microprocessor configuration data. Via Technologies, Richard K Huffman, James W Huffman, March 17, 2015: US08982655 (19 worldwide citation)

An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed conf ...


5
Gerard M Col, G Glenn Henry, Dinesh K Jain: Apparatus and method for speculatively updating global branch history with branch prediction prior to resolution of branch outcome. IP First, E Alan Davis, James W Huffman, February 25, 2003: US06526502 (18 worldwide citation)

An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A dynamic branch predictor speculatively updates global branch history information based on the prediction of a first branch instruction so that the p ...


6
Dinesh K Jain, Albert J Loper Jr, Arturo Martin de Nicolas: Concurrent execution of divide microinstructions in floating point unit and overflow detection microinstructions in integer unit for integer divide. IP First, Richard K Huffman, James W Huffman, May 9, 2000: US06061781 (14 worldwide citation)

An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequen ...


7
Rodney E Hooker, Dinesh K Jain, Terry Parks: Method and apparatus for speculative microinstruction pairing. IP First, E Alan Davis, James W Huffman, August 19, 2003: US06609191 (6 worldwide citation)

An apparatus and method are provided for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor and subsequently splitting the paired micro instructions in the same clock cycle as the pairing if a resource conflict or operand dependency is detect ...


8
G Glenn Henry, Dinesh K Jain: Apparatus and method for tamper protection of a microprocessor fuse array. VIA Technologies, Richard K Huffman, James W Huffman, December 25, 2012: US08341472 (2 worldwide citation)

An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configu ...


9
G Glenn Henry, Dinesh K Jain: Apparatus and method for storage and decompression of configuration data. VIA ALLIANCE SEMICONDUCTOR, Richard K Huffman, James W Huffman, July 25, 2017: US09715456 (1 worldwide citation)

An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a plurality of semiconductor fuses that are programmed with compressed confi ...


10
G Glenn Henry, Dinesh K Jain: Apparatus and method for extended cache correction. VIA ALLIANCE SEMICONDUCTOR, Richard K Huffman, James W Huffman, July 18, 2017: US09710390

An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compre ...