1
Dimitris Pantelakis, Kerry Tedrow: Method and apparatus for regulating the output voltage of negative charge pumps. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 3, 1996: US05553295 (72 worldwide citation)

A regulation circuit which includes circuitry for furnishing a reference voltage, a voltage divider for furnishing a voltage provided by a charge pump circuit, a comparator for comparing the output of the charge pump circuit with the reference voltage, and apparatus for operating the charge pump whe ...


2
Dimitris Pantelakis, Kerry Tedrow, Johnny Javanifard, George Canepa: Method and apparatus for providing an ultra low power regulated negative charge pump. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 2, 1996: US05532915 (17 worldwide citation)

A circuit for providing a regulated output voltage from a charge pump circuit while utilizing very low amounts of power, the circuit including a clock circuit for providing clock pulses to operate the charge pump circuit to produce an output voltage, a bias circuit for monitoring the output voltage ...


3
John L Melanson, Dimitris Pantelakis, Robert A Jensen, Vikram Shenoy: Circuit and method for stress testing a static random access memory (SRAM) device. Cirrus Logic, Steven Lin Esq, December 31, 2002: US06501692 (16 worldwide citation)

A stress test circuit and method for static random access memory (“SRAM”) cells of an SRAM device are disclosed. The stress test component has a resistance element and a switch component to electrically couple the resistance element between a bit line and complementary bit line of an SRAM cell stori ...


4
Manuel Antonio D Abreu, Dimitris Pantelakis, Stephen Skala: System and method of determining a programming step size for a word line of a memory. SanDisk Technologies, Toler Law Group PC, May 27, 2014: US08737130 (8 worldwide citation)

A method includes determining a programming step size for a word line of a memory in a data storage device. The programming step size is determined at least partially based on a count of memory elements of the word line to be programmed to a particular state.


5
Manuel Antonio D Abreu, Dimitris Pantelakis, Stephen Skala: Tracking cell erase counts of non-volatile memory. SANDISK TECHNOLOGIES, Toler Law Group PC, October 6, 2015: US09153331 (5 worldwide citation)

A data storage device includes a memory and a controller and may perform a method that includes updating, in a controller of the data storage device, a value of a particular write/erase (W/E) counter of a set of counters in response to an erase operation to a particular region of the non-volatile me ...


6
Dimitris Pantelakis: Method and apparatus for generating four phase non-over lapping clock pulses for a charge pump. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 25, 1997: US05692164 (4 worldwide citation)

A clock generation circuit which includes a first circuit for generating first and second trains of non-overlapping and opposite phase clock pulses from an input train of clock pulses, and second and third circuits each for generating a pair of non-overlapping and opposite phase trains of clock puls ...


7
Robert Arthur Jensen, Mail Khoi, Vikram Shenoy, Dimitris Pantelakis: Glitch-free memory address decoding circuits and methods and memory subsystems using the same. Cirrus Logic, Thompson & Knight, April 18, 2006: US07032083 (4 worldwide citation)

Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received address bits for presentation to the inputs of the decoder and includes reset circuitry for resetting the ou ...


8
Anup Nayak, Dimitris Pantelakis, Fariborz Golshani, Derwin Mattos: Asynchronous arbiter with bounded resolution time and predictable output state. Cypress Semiconductor Corporation, Haverstock & Owens, May 29, 2007: US07225283 (2 worldwide citation)

An arbiter circuit (100) can include a latch (106) that latches competing input signals (Req_A and Req_B) to generate latch output signals (latn1 and latn2). A filter section (108) can prevent metastable states of latch output signals (latn1 and latn2) from propagating through to output signals (Sel ...


9
Manuel Antonio D Abreu, Dimitris Pantelakis, Stephen Skala: System and method of adjusting a programming step size for a block of a memory. Sandisk Technologies, Toler Law Group PC, September 16, 2014: US08838883 (2 worldwide citation)

A method includes decreasing a programming step size from a first value to a second value for a block of a memory device. The programming step size is decreased at least partially based on determining that an error count corresponding to the block satisfies a threshold.


10
Manuel Antonio D Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi: Smart bridge for memory core. SANDISK TECHNOLOGIES, Toler Law Group PC, December 22, 2015: US09218852 (1 worldwide citation)

An apparatus includes a first semiconductor device including a memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the memory core. The second semiconductor device includes a second serializer/deserializer communication interface coupl ...