1
Xavier Baie
Bruce B Doris, Dureseti Chidambarrao, Xavier Baie, Jack A Mandelman, Devendra K Sadana, Dominic J Schepis: SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device. International Business Machines Corporation, Jay H Anderson, Whitham Curtis & Christofferson P C, April 6, 2004: US06717216 (146 worldwide citation)

Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET devices, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in ...


2
Xavier Baie
Bruce B Doris, Dureseti Chidambarrao, Xavier Baie, Jack A Mandelman, Devendra K Sadana, Dominic J Schepis: Field effect transistor with stressed channel and method for making same. International Business Machines Corporation, Whitham Curtis & Christofferson P C, Jay H Anderson, April 26, 2005: US06884667 (18 worldwide citation)

Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET device, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in ...


3
Katherina Babich
Katherina E Babich, Bruce B Doris, David R Medeiros, Devendra K Sadana: Method for tuning epitaxial growth by interfacial doping and structure including same. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, September 7, 2010: US07790593

A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of ...


4
Katherina Babich
Katherina E Babich, Bruce B Doris, David R Medeiros, Devendra K Sadana: Method for tuning epitaxial growth by interfacial doping and structure including same. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Robert M Trepp Esq, February 12, 2008: US07329596

A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of ...


5
Katherina Babich
Katherina E Babich, Bruce B Doris, David R Medeiros, Devendra K Sadana: Method for tuning epitaxial growth by interfacial doping and structure including same. International Business Machines Corporation, Scully Scott Murphy & Presser PC, April 26, 2007: US20070090487-A1

A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of ...


6
Katherina Babich
Thomas N Adam, Katherina E Babich, Stephen W Bedell, Joel P de Souza, Gerald W Gibson, Alexander Reznicek, Devendra K Sadana, Seshadri Subbanna: Selective epitaxial growth by incubation time engineering. International Business Machines Corporation, November 22, 2012: US20120295417-A1

A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth ...


7
Katherina Babich
Katherina E Babich, Bruce B Doris, David R Medeiros, Devendra K Sadana: Method for tuning epitaxial growth by interfacial doping and structure including same. International Business Machines Corporation, Scully Scott Murphy & Presser PC, April 24, 2008: US20080093640-A1

A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of ...


8
Katherina Babich
Katherina E Babich, Bruce B Doris, David R Medeiros, Devendra K Sadana: Method for tuning epitaxial growth by interfacial doping and structure including same. International Business Machines Corporation, Scully Scott Murphy & Presser PC, June 26, 2008: US20080153270-A1

A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of ...


9
David M Fried, Edward J Nowak, Beth A Rainey, Devendra K Sadana: Fin FET devices from bulk semiconductor and method for forming. International Business Machines Corporation, Mark F Chadurjian, Schmeiser Olsen & Watts, November 4, 2003: US06642090 (292 worldwide citation)

The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while ...


10
Carl J Radens, Gary B Bronner, Tze chiang Chen, Bijan Davari, Jack A Mandelman, Dan Moy, Devendra K Sadana, Ghavam Ghavami Shahidi, Scott R Stiffler: Silicon-on-insulator vertical array device trench capacitor DRAM. International Business Machines Corporation, H Daniel Schnurmann, May 20, 2003: US06566177 (164 worldwide citation)

A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate ...



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