1
Deepraj S Puar: Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad. NeoMagic, Stuart T Auvinen, April 9, 1996: US05506499 (93 worldwide citation)

Each touchdown of a probe card during wafer-sort testing of integrated circuits can leave a gouge in the pad metal. These gouges reduce the reliability of any wire bond to that pad as voids can be left in the bond where the gouges are. A second auxiliary test pad is adjacent to the primary bonding p ...


2
Deepraj S Puar: Depletion-mode FET for the regulation of the on-chip generated substrate bias voltage. Signetics Corporation, R J Meetin, J Oisher, T Briody, April 19, 1988: US04739191 (92 worldwide citation)

An on-chip regulated substrate bias voltage generator for an MOS integrated circuit includes a ring oscillator (10) for developing a true signal and its complement. The signals are applied to a charge pump (12) that includes two capacitors (C1 and C2) and a plurality of rectifiers (22, 24, and 26). ...


3
Deepraj S Puar: Semiconductor memory array. Signetics Corporation, Jerry A Dinardo, Robert T Mayer, Thomas A Briody, July 27, 1982: US04342102 (67 worldwide citation)

An improved read-only memory arrangement for generating a differential output signal within the memory array itself incorporates a column of reference cell transistors and a single reference bit line within the same general area occupied by the memory cell transistors and memory main bit lines. Each ...


4
Deepraj S Puar: Shunt circuit for electrostatic discharge protection. Cirrus Logic, Blakely Sokoloff Taylor & Zafman, February 15, 1994: US05287241 (49 worldwide citation)

A circuit is added to a complementary metal-oxide silicon (CMOS) integrated circuit (IC) to provide an intentional, non-reverse-biased VDD-to-VSS shunt path for transient currents such as electrostatic discharges (ESD). This circuit protects the IC from ESD damage by turning on before any other path ...


5
Deepraj S Puar, Ravi Ranganathan: Graphics controller integrated circuit without memory interface. NeoMagic Corporation, Townsend and Townsend and Crew, July 22, 1997: US05650955 (41 worldwide citation)

A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for recei ...


6
Deepraj S Puar, Ravi Ranganathan: Graphics controller integrated circuit without memory interface. NeoMagic Corporation, Townsend and Townsend and Crew, December 30, 1997: US05703806 (34 worldwide citation)

A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for recei ...


7
Ravi Ranganathan, Deepraj S Puar: Dynamic logic having power-down mode with periodic clock refresh for a low-power graphics controller. NeoMagic, Stuart T Auvinen, December 24, 1996: US05587672 (27 worldwide citation)

A controller chip has dynamic logic which is driven by a suspendable clock. Power is reduced in a standby mode when the clock to the dynamic logic is stopped. However, power is still applied to the dynamic logic in standby mode so that the dynamic logic can be quickly resumed without the delay of re ...


8
Deepraj S Puar, Ravi Ranganathan: Graphics controller integrated circuit without memory interface. NeoMagic Corporation, Gary T Aka, March 12, 2002: US06356497 (27 worldwide citation)

A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for recei ...


9
Deepraj S Puar, Ravi Ranganathan: Graphics controller integrated circuit without memory interface pins and associated power dissipation. NeoMagic Corporation, Townsend and Townsend and Crew, March 21, 2000: US06041010 (23 worldwide citation)

A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for recei ...


10
Deepraj S Puar: Input protection device for integrated circuits. North American Philips Corporation Signetics Division, R Meetin, D Treacy, T Briody, November 22, 1988: US04786956 (22 worldwide citation)

A device (16) for preventing an input signal (V.sub.I) applied to a terminal (12) of an integrated circuit from damaging a section (18) of the circuit contains a regular enhancement-mode insulated-gate FET (Q1 or Q2), a resistor (R1 or R2) that enables the regular FET to act temporarily like a "floa ...