1
Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J Adiletta: Mapping requests from a processing unit that uses memory-mapped input-output space. Intel Corporation, Fish & Richardson P C, February 17, 2004: US06694380 (147 worldwide citation)

A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a correspon ...


2
Gilbert Wolrich, Debra Bernstein, Donald Hooper, Matthew J Adiletta, William Wheeler: Thread signaling in multi-threaded network processor. Intel Corporation, Fish & Richardson P C, September 23, 2003: US06625654 (120 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory cont ...


3
Debra Bernstein, Donald F Hooper, Matthew J Adiletta, Gilbert Wolrich, William Wheeler: Microengine for parallel processor architecture. Intel Corporation, Fish & Richardson P C, December 23, 2003: US06668317 (112 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory con ...


4
Gilbert Wolrich, Debra Bernstein, Matthew J Adiletta, Donald F Hooper: Method and apparatus for gigabit packet assignment for multithreaded packet processing. Intel Corporation, Fish & Richardson P C, December 9, 2003: US06661794 (93 worldwide citation)

A network processor that has multiple processing elements, each processing element supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. E ...


5
Gilbert Wolrich, Debra Bernstein, Matthew J Adiletta, William Wheeler: Arbitrating command requests in a parallel multi-threaded processing system. Intel Corporation, Fish & Richardson P C, March 11, 2003: US06532509 (88 worldwide citation)

A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on t ...


6
Gilbert Wolrich, Debra Bernstein, Matthew J Adiletta, William Wheeler: Handling contiguous memory references in a multi-queue system. Intel Corporation, Fish & Richardson P C, May 6, 2003: US06560667 (74 worldwide citation)

A controller for a random access memory has control logic, including an arbiter that detects a status of outstanding memory references. The controller selects a memory reference from one of a plurality queues of memory references. The control logic is responsive to a memory reference chaining bit th ...


7
Mark B Rosenbluth, Gilbert Wolrich, Debra Bernstein: Software controlled content addressable memory in a general purpose execution datapath. Intel Corporation, Fish & Richardson P C, March 15, 2005: US06868476 (73 worldwide citation)

A lookup mechanism provides an input value to a datapath element disposed in an execution datapath of a processor and causes the datapath element to compare the input value to stored identifier values. The lookup mechanism receives from the datapath element a result based on the comparison.


8
Gilbert Wolrich, Debra Bernstein, Matthew Adiletta: Method and apparatus for sharing access to a bus. Intel Corporation, Fish & Richardson P C, October 8, 2002: US06463072 (70 worldwide citation)

A router includes a communications bus, a second bus, and at least two processors. The second bus transfers ready status data from ports connected to the communications bus. The processors are connected to the communications and second busses. One of the processors controls the communications bus at ...


9
Gilbert Wolrich, Debra Bernstein, Matthew Adiletta: Scratchpad memory. Intel Corporation, Fish & Richardson P C, December 23, 2003: US06667920 (69 worldwide citation)

An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.


10
Gilbert Wolrich, Daniel Cutter, William Wheeler, Matthew J Adiletta, Debra Bernstein: Read lock miss control and queue management. Intel Corporation, Fish & Richardson P C, November 27, 2001: US06324624 (68 worldwide citation)

Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if (1) the read lock memory reference request is requesting access to an unlocked memory location and (2) the ...