21
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia: PCI express enhancements and extensions. Intel Corporation, David P McAbee, March 1, 2011: US07899943 (10 worldwide citation)

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Messa ...


22
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia: PCI express enhancements and extensions. Intel Corporation, David P McAbee, December 6, 2011: US08073981 (10 worldwide citation)

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Messa ...


23
Debendra Das Sharma, Sharon M Ebner, John A Wickeraad, Joe P Cowan, Carl H Jackson: Using read current transactions for improved performance in directory-based coherent I/O systems. Hewlett Packard Development Company, November 11, 2003: US06647469 (10 worldwide citation)

A shared memory provides data access to a plurality of agents (e.g., processor, cells of processors, I/O controllers, etc.) and includes a memory and a memory controller. The memory controller selectively provides memory access to the agents in both coherent and read current modes of operation. In t ...


24
Sharon M Ebner, Debendra Das Sharma: Arbitration scheme for equitable distribution of bandwidth for agents with different bandwidth requirements. Hewlett Packard Development Company, July 15, 2003: US06594718 (10 worldwide citation)

A device for arbitrating access to a resource by a plurality of agents includes logic configured to associate requesting ones of the agents with access tokens. The number of the access tokens assigned to each requesting agent is proportional to its bandwidth or speed in comparison with the other req ...


25
Debendra Das Sharma: Method and apparatus for improving system performance through remote credit management. Hewlett Packard Development Company, September 5, 2006: US07103672 (9 worldwide citation)

A method and apparatus are disclosed for improving system performance by controlling the flow of transactions between interconnected nodes by considering the system resources required for a transaction response when determining whether to send a transaction. The system uses a debit system for tracki ...


26
Debendra Das Sharma, Ajay V Bhatt: Using asymmetric lanes dynamically in a multi-lane serial link. Intel Corporation, Derek J Reynolds, October 5, 2010: US07809969 (9 worldwide citation)

A method, device, and system are disclosed. In one embodiment, the method comprises transitioning one or more lanes of a multi-lane serial link from a fully operational power state to a low power state and keeping one or more other lanes of the multi-lane serial link in the fully operational power s ...


27
Debendra Das Sharma: Using page registers for efficient communication. Hewlett Packard Company, September 4, 2001: US06285686 (8 worldwide citation)

The inventive mechanism reduces the bandwidth required to transmit an information packet. The inventive mechanism uses page registers that store the bit patterns that are likely to repeat. The information includes a reference to the stored pattern in place of the pattern. Both the receiving node and ...


28
Debendra Das Sharma: System and method for efficient communication between buses. Hewlett Packard Company, June 13, 2000: US06076130 (8 worldwide citation)

The inventive mechanism has a bypassable transaction that is directly loaded to the bypass queue. For example, all read transactions from a PCI bus are directly loaded to the bypass queue. This avoids the route through the common queue to the bypass queue for a read transaction that cannot be loaded ...


29
Myeong S Lee, Debendra Das Sharma, Jon Bock: Method and apparatus for evaluating a circuit. Hewlett Packard Company, April 29, 2003: US06557147 (8 worldwide citation)

An apparatus and method for performance counter verification of an electronic circuit. The apparatus and method sends a transaction to a circuit under test causing counter values to change and retrieves these counter values from the circuit under test for comparison with known or expected counter va ...


30
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia: PCI express enhancements and extensions. Intel Corporation, Patent Capital Group, October 1, 2013: US08549183 (7 worldwide citation)

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Messa ...