1
Len Schultz, Nhon Toai Quach, Dean Mulla, Jim Hays, John Fu: Method of correcting a machine check error. Intel Corporation, Blakely Sokoloff Taylor and Zafman, September 20, 2005: US06948094 (123 worldwide citation)

Processor implementation-specific instructions save a processor state in a system memory and attempt to correct the error. Control is then transferred to processor-independent instructions. Control is returned to the processor implementation-specific instructions which then return to an interrupted ...


2
Dean Mulla, Sorin Iacobovici: Cache arrangement including coalescing buffer queue for non-cacheable data. Institute for the Development of Emerging Architectures L L C, Jack A Lenell, September 2, 1997: US05664148 (48 worldwide citation)

An apparatus including a cache subsystem arrangement for efficient management of input/output operations and of memory shared by processors in a multiprocessor system. The apparatus includes a central processing unit, an input/output device such as a network device or a display device for example, a ...


3
Dean Mulla, Sorin Iacobovici: Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues. Institute for the Development of Emerging Architectures L L C, Jack A Lenell, July 29, 1997: US05652859 (47 worldwide citation)

A method and apparatus for snooping both cache memory and associated buffer queues in a cache subsystem arrangement. Since there are usually several requests for cache data being handled at any given time under high performance operation of multiple processors, a cache arrangement includes at least ...


4
Nhon Toai Quach, John Fu, Sunny Huang, Jeen Miin, Dean Mulla: Combined tag and data ECC for enhanced soft error recovery from cache tag errors. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 3, 2004: US06772383 (37 worldwide citation)

A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol and an error correction code. The error correction code provides error correction for a thi ...


5
Nhon Toai Quach, John Fu, Sunny Huang, Jeen Miin, Dean Mulla: Combined tag and data ECC for enhanced soft error recovery from cache tag errors. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 20, 2008: US07376877 (11 worldwide citation)

A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol different from the first symbol and an error correction code. The error correction code pro ...


6
Krishnakanth Sistla, Dean Mulla, Vivek Garg, Mark Rowland, Suresh Doraiswamy, Ganapati Srinivasa, Jeffrey D Gilbert: Dynamically adjusting power of non-core processor circuitry including buffer circuitry. Intel Corporation, Trop Pruner & Hu P C, November 22, 2016: US09501129 (1 worldwide citation)

In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure ...


7
Vivek Garg, Alexander Gendler, Arvind Raman, Ashish V Choubal, Krishnakanth V Sistla, Dean Mulla, Eric J Dehaemer, Rahul Agrawal, Guy G Sotomayor: Controlling telemetry data communication in a processor. Intel Corporation, Trop Pruner & Hu P C, March 6, 2018: US09910470

In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a s ...


8
Alexander Gendler, Larisa Novakovsky, Krishnakanth V Sistla, Vivek Garg, Dean Mulla, Ashish V Choubal, Erik G Hallnor, Kimberly C Weier: Masking a power state of a core of a processor. Intel Corporation, Trop Pruner & Hu P C, July 18, 2017: US09710041

In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the ...


9
Krishnakanth Sistla, Dean Mulla, Vivek Garg, Mark Rowland, Suresh Doraiswamy, Ganapati Srinivasa, Jeffrey D Gilbert: Dynamically adjusting power of non-core processor circuitry including buffer circuitry. Intel Corporation, Trop Pruner & Hu P C, December 16, 2014: US08914650

In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure ...


10
Nazar S Haider, Dean Mulla, Allen W Chu: Systems and methods for core droop mitigation based on license state. INTEL CORPORATION, Stoel Rives, September 5, 2017: US09753525

Systems, methods, and devices are disclosed for mitigating voltage droop in a computing device. An example apparatus includes a plurality of threshold registers to store respective voltage droop thresholds, and an interface to receive a license grant message indicating a license mode for a processor ...