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David V Chudnovsky, Gregory V Chudnovsky: Method to resolve an incorrectly entered uniform resource locator (URL). David Chudnovsky, Gregory Chudnovsky, Dov Rosenfeld, Inventek, May 20, 2008: US07376752 (43 worldwide citation)

A method and a carrier medium carrying code segments to cause a processor to implement a method for resolving a possibly incorrectly entered URL. The method includes accepting the entered URL, parsing the accepted URL into URL parts, and carrying out a conventional URL lookup. In one embodiment, for ...


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Gregory V Chudnovsky, David V Chudnovsky: Multi-bank, fault-tolerant, high-performance memory addressing system and method. February 11, 2003: US06519673 (19 worldwide citation)

A memory addressing system for a multi-bank device that generally provides no band conflicts for stride


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Gregory V Chudnovsky, David V Chudnovsky: Multi-bank, fault-tolerant, high-performance memory addressing system and method. Pennie & Edmonds, April 30, 2002: US06381669 (10 worldwide citation)

A memory addressing system for a multi-bank memory device that generally provides no bank conflicts for stride 1 data access patterns and infrequent ban conflicts for power of 2 stride patterns or other access patterns of interest. In a preferred embodiment, the device comprises an address translati ...


4
Gregory V Chudnovsky, David V Chudnovsky: Multi-bank, fault-tolerant, high-performance memory addressing system and method. Jones Day, June 8, 2004: US06748480 (6 worldwide citation)

A memory addressing system for a multi-bank memory device that generally provides no bank conflicts for stride 1 data access patterns and infrequent bank conflicts for power of 2 stride patterns or other access patterns of interest. In a preferred embodiment, the device comprises an address translat ...


5
Gregory V Chudnovsky, David V Chudnovsky: Multi-bank, fault-tolerant, high-performance memory addressing system and method. Pennie And Edmonds, September 25, 2003: US20030182491-A1

A memory addressing system for a multi-bank memory device that generally provides no bank conflicts for stride 1 data access patterns and infrequent bank conflicts for power of 2 stride patterns or other access patterns of interest. In a preferred embodiment, the device comprises an address translat ...


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