1
Syed M Alam, Ibrahim M Elfadel, Kathryn W Guarini, Meikei Ieong, Prabhakar N Kudva, David S Kung, Mark A Lavin, Arifur Rahman: Three dimensional integrated circuit. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Rafael Perez Piniero Esq, December 25, 2007: US07312487 (117 worldwide citation)

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to ...


2
Jun Dong Cho, David S Kung: Timing-driven global placement based on geometry-aware timing budgets. International Business Machines Corporation, F Chau & Associates, November 12, 2002: US06480991 (95 worldwide citation)

A system and method for timing-closed placement which also takes wirelength and congestion into consideration. In one aspect, the system and method of timing driven placement according to the present invention incorporates a timing budget management technique which satisfies triangle parity and ineq ...


3
Syed M Alam, Ibrahim M Elfadel, Kathryn W Guarini, Meikei Ieong, Prabhakar N Kudva, David S Kung, Mark A Lavin, Arifur Rahman: Three dimensional integrated circuit and method of design. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Brian P Verminski Esq, May 25, 2010: US07723207 (85 worldwide citation)

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to ...


4
William R Migatz, Paul M Campbell, David J Hathaway, David S Kung, Ruchir Puri, Louise H Trevillyan: Clock tree distribution generation by determining allowed placement regions for clocked elements. International Business Machines Corporation, H Daniel Schnurmann, May 29, 2007: US07225421 (19 worldwide citation)

A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining an ...


5
Nathaniel Hieter, David J Hathaway, Prabhakar Kudva, David S Kung, Leon Stok: Method for performing timing closure on VLSI chips in a distributed environment. International Business Machines Corporation, H Daniel Schnurmann, February 13, 2007: US07178120 (15 worldwide citation)

A method for performing timing closure on VLSI chips in a distributed environment is described. Abstracting the physical and timing resources of a chip and providing an asynchronous method of updating that abstraction allows multiple partitions of a chip to be optimized concurrently. A global view o ...


6
Anthony Correale Jr, Rajiv V Joshi, David S Kung, Zhigang Pan, Ruchir Puri: Single supply level converter. International Business Machines, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Satheesh K Karra Esq, October 10, 2006: US07119578 (12 worldwide citation)

A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. T ...


7
Anthony Correale Jr, David S Kung, Douglass T Lamb, Zhigang Pan, Ruchir Puri, David Wallach: Multiple voltage integrated circuit and design method therefor. International Business Machines, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Satheesh K Karra Esq, September 19, 2006: US07111266 (9 worldwide citation)

An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit ...


8
David S Kung: System and method for improving logic synthesis in logic circuits. International Business Machines Corporation, F Chau & Associates, June 26, 2001: US06253356 (9 worldwide citation)

A method of fanout optimization includes the steps of inputting a net list including fanout regions, each fanout region having sources, each source being coupled to at least one sink, determining a gain for inverters to be placed in a buffer tree, wherein the gain has a same value for all inverters ...


9
Anthony Correale Jr, David S Kung, Douglass T Lamb, Zhigang Pan, Ruchir Puri: Method and program product of level converter optimization. International Business Machines, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Satheesh K Karra Esq, August 8, 2006: US07089510 (7 worldwide citation)

A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) ...


10
Ruchir Puri, David S Kung, Anthony Drumm: System and method for fast interconnect delay estimation through iterative refinement. International Business Machines Corporation, Dilworth & Barrese, July 29, 2003: US06601223 (6 worldwide citation)

A system and method are proposed for estimating interconnect delay in an Integrated Circuit (IC). A formula for effective capacitance is derived which considers the effect of slew as well as resistive shielding of capacitance, thus yielding more accurate delays for both the interconnects and the sou ...



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