1
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John G Favor, Dale R Greenley, Robert A Cargnoni: Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags. Nexgen Microsystems, Townsend and Townsend Khourie and Crew, July 6, 1993: US05226126 (369 worldwide citation)

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report terminat ...


2
John G Favor, Korbin Van Dyke, David R Stiles: Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency. NexGen Microsystems, Townsend and Townsend Khourie and Crew, July 6, 1993: US05226130 (260 worldwide citation)

The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch pre ...


3
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John Gregory Favor, Dale R Greenley, Robert A Cargnoni: Method and apparatus for debugging an integrated circuit. Advanced Micro Devices, B Noël Kivlin, Conley Rose & Tayon PC, December 24, 2002: US06499123 (154 worldwide citation)

An integrated circuit having a normal mode for operating under normal operating conditions and a debug mode for operating to test and debug the integrated circuit. The integrated circuit includes a plurality of output pins that carry a first plurality of signals in the normal mode and carry a second ...


4
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John G Favor, Dale R Greenley, Robert A Cargnoni: Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts. NexGen, Townsend and Townsend Khourie and Crew, August 15, 1995: US05442757 (103 worldwide citation)

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report terminat ...


5
Korbin S Van Dyke, David R Stiles, John G Favor: Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence. NexGen Microsystems, Townsend and Townsend Khourie and Crew, July 20, 1993: US05230068 (102 worldwide citation)

A system which integrates the multiple instruction queues and the branch target cache (BTC) of a high performance CPU design into a single physical structure. Effectively, the queues are merged into the BTC in such a manner that, at any point in time, most of this structure functions as a BTC while ...


6
David R Stiles, John G Favor, Korbin S Van Dyke: Two-level branch prediction cache. Nexgen Microsystems, Townsend and Townsend, November 10, 1992: US05163140 (100 worldwide citation)

An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited numbe ...


7
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John Gregory Favor, Dale R Greenley, Robert A Cargnoni: Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions. Advanced Micro Devices, Townsend and Townsend and Crew, June 16, 1998: US05768575 (95 worldwide citation)

A pipeline control system for implementing a virtual architecture having complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These o ...


8
David R Stiles: Apparatus for superscalar instruction predecoding using cached instruction lengths. NexGen, Townsend and Townsend and Crew, April 30, 1996: US05513330 (52 worldwide citation)

A method and apparatus for eliminating the delay in a parallel processing pipeline. In a parallel processing pipeline system, a circuitry is provided to determine the length and align two instructions in parallel. Parallel decoding circuitry is provided for decoding and executing the two instruction ...


9
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John Gregory Favor, Dale R Greenley, Robert A Cargnoni: Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions. Advanced Micro Devices, Townsend and Townsend and Crew, July 14, 1998: US05781753 (50 worldwide citation)

A pipeline control system for implementing a virtual architecture having a complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These ...


10
David R Stiles, John G Favor, Korbin S Van Dyke: Two-level branch prediction cache. Nexgen, Townsend and Townsend and Crew, May 7, 1996: US05515518 (49 worldwide citation)

AN improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited numbe ...