1
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Multi-dice chip scale semiconductor components and wafer level methods of fabrication. Micron Technology, Stephen A Gratton, January 11, 2005: US06841883 (385 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


2
Salman Akram, David R Hembree, Warren M Farnworth: Micromachined chip scale package. Micron Technology, Task Britt & Rossa, June 6, 2000: US06072236 (242 worldwide citation)

A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the ...


3
Salman Akram, David R Hembree, Warren M Farnworth: Micromachined chip scale package. Micron Technology, Trask Britt & Rossa, September 26, 2000: US06124634 (180 worldwide citation)

A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the ...


4
Alan G Wood, Warren M Farnworth, David R Hembree: Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die. Micron Technology, Stanley N Protigal, Stephen A Gratton, April 18, 1995: US05408190 (170 worldwide citation)

A reusable burn-in/test fixture for discrete die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. Electrical contact with bondpads or bumps on the die is established through an intermediate substrate. When the two halves are assembled, electrical c ...


5
David R Hembree, Salman Akram: Semiconductor probe card having resistance measuring circuitry and method fabrication. Micron Technology, Stephen A Gratton, January 30, 2001: US06181144 (167 worldwide citation)

A probe card for testing semiconductor wafers, and a method for fabricating the probe card are provided. The probe card is adapted for use with a wafer probe handler, and a tester containing test circuitry. The probe card includes a substrate, and patterns of probe contacts formed on the substrate. ...


6
Warren M Farnworth, Alan G Wood, David R Hembree: Method for fabricating semiconductor components and interconnects with contacts on opposing sides. Micron Technology, Stephen A Gratton, September 16, 2003: US06620731 (159 worldwide citation)

A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The con ...


7
Alan G Wood, Warren M Farnworth, David R Hembree: Carrier for testing an unpackaged semiconductor die. Micron Technology, Stephen A Gratton, May 21, 1996: US05519332 (154 worldwide citation)

A carrier for testing an unpackaged semiconductor die is provided. The carrier includes a carrier base for supporting the die; an interconnect for establishing a temporary electrical connection with the die; and a force distribution mechanism for biasing the die and interconnect together. In an illu ...


8
Warren M Farnworth, Alan G Wood, David R Hembree: Semiconductor component and interconnect having conductive members and contacts on opposing sides. Micron Technology, Stephen A Gratton, June 7, 2005: US06903443 (148 worldwide citation)

A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The con ...


9
Alan G Wood, Warren M Farnworth, David R Hembree: Carrier for testing an unpackaged semiconductor die. Micron Technology, Stephen A Gratton, July 30, 1996: US05541525 (145 worldwide citation)

A carrier for testing an unpackaged semiconductor die is provided. The carrier includes: a base; a temporary interconnect for establishing electrical communication between the die and external test circuitry; a retention mechanism for securing the interconnect to the base; and a force distribution m ...


10
David R Hembree: Interposer for semiconductor components having contact balls. Micron Technology, Stephen A Gratton, June 5, 2001: US06242932 (141 worldwide citation)

An interposer for electrically engaging semiconductor components having contact balls is provided. In a testing embodiment, the interposer configures a test socket for testing semiconductor components with different configurations of contact balls. In an assembly embodiment, the interposer can be us ...



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