1
David R Hanson, Hance H Huston III, Kris V Srikrishnan: Process for restoring rejected wafers in line for reuse as new. International Business Machines Corporation, Tiffany L Townsend, Ratner & Prestia, July 6, 1999: US05920764 (85 worldwide citation)

A process applicable to the restoration of defective or rejected semiconductor wafers to a defect-free form uses etchants and a variation of the Smart-Cut.RTM. process. Because of the use of the variation on the Smart-Cut.RTM. process, diffusion regions are removed without significantly affecting th ...


2
David R Hanson: Machine independent debugger. Microsoft Corporation, Merchant & Gould, September 21, 2004: US06795962 (35 worldwide citation)

The present invention teaches a source-level debugger that defines symbol tables with a grammar. A grammar interface component is used by the compiler to automate portions of the debugger to construct and write the symbol table in a grammar thus simplifying the compiler. The grammar interface compon ...


3
Alan Wilson Langman, Michael R Inggs, Leendert Johannes du Toit, Kirankumar M Kothari, David R Hanson: Obstacle detection system for underground operations. Gas Technology Institute, Mark E Fejer, March 21, 2006: US07013991 (25 worldwide citation)

An obstacle avoidance system for obstacle detection in an opaque material. The system includes at least one electromagnetic signal source adapted to produce an electromagnetic source signal suitable for transmission through the opaque material, at least one electromagnetic signal detector adapted to ...


4
David R Hanson, Toshiaki Kirihata, Gerhard Mueller: Method of reducing sub-threshold leakage in circuits during standby mode. International Business Machines Corporation, February 18, 2003: US06522171 (17 worldwide citation)

A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after a precharge ...


5
David R Hanson, Toshiaki Kirihata, Gerhard Mueller: SDRAM with a maskable input. International Business Machines Corporation, Eric W Petraske, May 29, 2001: US06240043 (13 worldwide citation)

A random access memory (RAM) included in an integrated circuit and particularly a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and y bits wide corresponding to the number of data lines (DQs). An xy mask regis ...


6
Hoki Kim, Toshiaki Kirihata, David R Hanson, Gregory J Fredeman, John Golz: Dynamic random access memory with smart refresh scheduler. International Business Machines Corporation, Graham S Jones, H Daniel Schnurmann, October 11, 2005: US06954387 (10 worldwide citation)

In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit ...


7
Gerhard Mueller, David R Hanson: Mixed swing voltage repeaters for high resistance or high capacitance signal lines and methods therefor. Infineon Technologies North America, International Business Machines Corporation, Slater & Matsil, March 19, 2002: US06359471 (10 worldwide citation)

A mixed swing voltage repeater circuit operates with reduced voltage signals, that is signals having a voltage level that is below a full swing voltage level. The mixed swing voltage repeater circuit is configured to be coupled to the signal line and has an input node coupled to a first portion of t ...


8
Gerhard Mueller, David R Hanson: Full swing voltage input/full swing output bi-directional repeaters for high resistance or high capacitance bi-directional signal lines and methods therefor. Infineon Technologies, International Business Machines Corporation, Stanton C Braden, November 6, 2001: US06313663 (8 worldwide citation)

A bidirectional full swing voltage repeater implemented on a signal line of an integrated circuit, which includes a first enable node for providing a first enable signal and a second enable node for providing a second enable signal. There is included a first full-swing unidirectional repeater circui ...


9
Wolfgang Hokenmaier, Gunther Lehmann, Gerd Frankowsky, David R Hanson: Twisted bit-line compensation for DRAM having redundancy. Infineon Technologies North America, Daly Crowley & Mofford, May 27, 2003: US06570794 (7 worldwide citation)

A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to ...


10
David R Hanson, Dureseti Chidambarrao, Gregory J Fredeman, David M Onsongo: Programming and determining state of electrical fuse using field effect transistor having multiple conduction states. International Business Machines Corporation, Daryl K Neff, H Daniel Schnurmann, July 10, 2007: US07242239 (6 worldwide citation)

A circuit is provided which is operable to program an electrically alterable element, e.g., fuse or antifuse, to a programmed state and determine whether the electrically alterable element is in the programmed state or not. Such circuit includes a multiple conduction state field effect transistor (“ ...