1
David L Roper, James W Cady, James Wilder, James Douglas Wehrly Jr, Jeff Buchle, Julian Dowden: Pitch change and chip scale stacking system. Staktek Group, Andrews Kurth L, J Scott Denko, May 30, 2006: US07053478 (108 worldwide citation)

The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two int ...


2
James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr, Julian Dowden, Jeff Buchle: Chip scale stacking system and method. Staktek Group, June 10, 2003: US06576992 (105 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, a pair of CSPs is stacked, with one CSP above the other. The two CS ...


3
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Group, Andrews Kurth, July 5, 2005: US06914324 (73 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...


4
James W Cady, Julian Partridge, James Douglas Wehrly Jr, James Wilder, David L Roper, Jeff Buchle: Low profile chip scale stacking system and method. Staktek Group, Andrews Kurth, J Scott Denko, April 11, 2006: US07026708 (64 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile contacts are created by any of a variety of methods and materials. A consolidated low profile contact structure and technique is provided fo ...


5
James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr: Integrated circuit stacking system and method. Staktek Group, Andrews Kurth, J Scott Denko, October 18, 2005: US06956284 (61 worldwide citation)

The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred e ...


6
James W Cady, Julian Partridge, James Douglas Wehrly Jr, James Wilder, David L Roper, Jeff Buchle: Low profile chip scale stacking system and method. Staktek Group, Andrew Kurth, J Scott Denko, August 22, 2006: US07094632 (39 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by ...


7
James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr: Flex-based circuit module. Entorian Technologies, Fish & Richardson P C, September 29, 2009: US07595550 (28 worldwide citation)

A form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design that is disposed about the form. In a preferred embodiment, the form standard will be d ...


8
Julian Partridge, James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr: Low profile stacking system and method. Staktek Group, Fish & Richardson P C, J Scott Denko, February 20, 2007: US07180167 (28 worldwide citation)

The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher tempe ...


9
James W Cady, James Wilder, David L Roper, Russell Rapport, James Douglas Wehrly Jr, Jeffrey Alan Buchle: Integrated circuit stacking system and method. Staktek Group, Andrews Kurth L, September 6, 2005: US06940729 (26 worldwide citation)

The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leade ...


10
Russell Rapport, James W Cady, James Wilder, David L Roper, James Douglas Wehrly Jr, Jeff Buchle: Memory expansion and chip scale stacking system and method. Staktek Group, Andrews Kurth, J Scott Denko, October 18, 2005: US06955945 (7 worldwide citation)

The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided her ...