1
William F Baxter, Robert G Gelinas, James M Guyer, Dan R Huck, Michael F Hunt, David L Keating, Jeff S Kimmell, Phil J Roux, Liz M Truebenbach, Rob P Valentine, Pat J Weiler, Joseph Cox, Barry E Gillott, Andrea Heyda, Rob J Pike, Tom V Radogna, Art A Sherman, Michael Sporer, Doug J Tucker, Simon N Yeung: Bus arbitration system for multiprocessor architecture. Data General Corporation, Sewall P Bronstein, William J Dike Bronstein Roberts & Cushman Daley Jr, February 15, 2000: US06026461 (86 worldwide citation)

A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure ...


2
William F Baxter, Robert G Gelinas, James M Guyer, Dan R Huck, Michael F Hunt, David L Keating, Jeff S Kimmell, Phil J Roux, Liz M Truebenbach, Rob P Valentine, Pat J Weiler, Joseph Cox, Barry E Gillott, Andrea Heyda, Rob J Pike, Tom V Radogna, Art A Sherman, Michael Sporer, Doug J Tucker, Simon N Yeung: Symmetric multiprocessing computer with non-uniform memory access architecture. Data General Corporation, Brian L Michaelis, David D Lowry, Sewell P Bronstein, March 23, 1999: US05887146 (81 worldwide citation)

A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure ...


3
William F Baxter, Robert G Gelinas, James M Guyer, Dan R Huck, Michael F Hunt, David L Keating, Jeff S Kimmell, Phil J Roux, Liz M Truebenbach, Rob P Valentine, Pat J Weiler, Joseph Cox, Barry E Gillott, Andrea Heyda, Rob J Pike, Tom V Radogna, Art A Sherman, Micheal Sporer, Doug J Tucker, Simon N Yeung: High availability computer system and methods related thereto. Data General Corporation, Sewall P Bronstein, William J Daley Jr, Dike Bronstein Roberts & Cushman, September 19, 2000: US06122756 (32 worldwide citation)

A high availability computer system and methodology including a backplane, having at least one backplane communication bus and a diagnostic bus, a plurality of motherboards, each interfacing to the diagnostic bus. Each motherboard also includes a memory system including main memory distributed among ...


4
James M Guyer, David I Epstein, David L Keating: Data processing system with unique microcode control. Data General, Gerald Cechony, Joel Wall, May 27, 1986: US04591972 (31 worldwide citation)

A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an ...


5
James M Guyer, David I Epstein, David L Keating, Walker Anderson, James E Veres, Harold R Kimmens: Method and apparatus for enhancing the operation of a data processing system. Data General, Gerald Cechony, Joel Wall, June 24, 1986: US04597041 (21 worldwide citation)

A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an ...


6
Mark D Hummel, James M Guyer, David I Epstein, David L Keating, Steven J Wallach: Digital data processing system having dual-purpose scratchpad and address translation memory. Data General, Gerald Cechony, Joel Wall, February 4, 1986: US04569018 (20 worldwide citation)

A data processing uses instructions which may refer to operands in main memory by either physical or logical addresses. The central processor has an internal memory organized as two portions. The first portion provides a scratchpad memory function for the central processor and the second portion is ...


7
James B Stein, David L Keating, Richard W Reeves: Unconditional wide branch instruction acceleration. Data General Corporation, Robert F O Connell, October 13, 1992: US05155818 (10 worldwide citation)

A method and system for handling a branch instruction which requires branching from a current instruction of a first instruction sequence to the first instruction of a second instruction sequence. The branch instruction is fetched and the next instruction of the first sequence is fetched while the b ...


8
Steven Wallach, Kenneth D Holberger, David L Keating, Steven M Staudaher: Hierarchial memory ring protection system using comparisons of requested and previously accessed addresses. Data General Corporation, Robert F O Connell, October 11, 1983: US04409655 (4 worldwide citation)

A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses. The system uses hierarchical memory storage using in a particular embodiment eight storage segments (rings), access to the rings being ...