1
David K Poulsen, Paul M Petersen, Sanjiv M Shah: Software implemented method for automatically validating the correctness of parallel computer programs. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 4, 2001: US06286130 (69 worldwide citation)

A software-implemented method for validating the correctness of parallel computer programs, written in various programming languages, with respect to these programs' corresponding sequential computer programs. Validation detects errors that could cause parallel computer programs to behave incor ...


2
David K Poulsen, Paul M Petersen, Sanjiv M Shah: Software implemented method for thread-privatizing user-specified global storage objects in parallel computer programs via program transformation. Kuck & Associates, Brinks Hofer Gilson & Lione, September 22, 1998: US05812852 (36 worldwide citation)

A software-implemented method for dynamically and statically privatizing global storage objects in parallel computer programs written in various programming languages. Privatization is accomplished via transformation of these parallel computer programs under the control of a general purpose computer ...


3
Ryan Rakvic, Richard A Hankins, Ed Grochowski, Hong Wang, Murali Annavaram, David K Poulsen, Sanjiv Shah, John Shen, Gautham Chinya: Load balancing for multi-threaded applications via asymmetric power throttling. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 31, 2012: US08108863 (24 worldwide citation)

A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to t ...


4
Hong Wang, Gautham N Chinya, Richard A Hankins, Shivnandan D Kaushik, Bryant Bigbee, John Shen, Per Hammarlund, Xiang Zou, Jason W Brandt, Prashant Sethi, Douglas M Carmean, Baiju V Patel, Scott Dion Rodgers, Ryan N Rakvic, John L Reid, David K Poulsen, Sanjiv M Shah, James Paul Held, James Charles Abel: Sequencer address management. Intel Corporation, David P McAbee, June 22, 2010: US07743233 (12 worldwide citation)

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses ...


5
David K Poulsen, Sanjiv M Shah, Paul M Petersen, Grant E Haab: Method and apparatus for an atomic operation in a parallel computing environment. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 14, 2004: US06792599 (5 worldwide citation)

A method and apparatus for a atomic operation is described. A method comprises receiving a first program unit in a parallel computing environment, the first program unit including a memory update operation to be performed atomically, the memory update operation having an operand, the operand being o ...


6
Richard A Hankins, Gautham N Chinya, Hong Wang, David K Poulsen, Shirish Aundhe, John P Shen, Sanjiv M Shah, Baiju V Patel: Data structure and management techniques for local user-level thread data. Intel Corporation, Barre Law Firm PLLC, December 13, 2011: US08079035 (3 worldwide citation)

Data structure creation, organization and management techniques for data local to user-level threads are provided. In one embodiment, a method includes generating, for a user-level thread (“shred”) to run on a thread unit that is not managed by an operating system (“OS”), a storage area for local da ...


7
William R Magro, David K Poulsen, Alexander V Supalov, Andrey B Derbunovich: Method and apparatus for transparent selection of alternate network interfaces in a message passing interface (“MPI”) implementation. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 5, 2010: US07644130 (2 worldwide citation)

A message passing interface (“MPI”) cluster may be initialized and configured by reading a list of node identifiers from a file, starting a process on each node whose identifier was listed, and providing a second list of node identifiers to the process.


8
Ryan Rakvic, Richard A Hankins, Ed Grochowski, Hong Wang, Murali Annavaram, David K Poulsen, Sanjiv Shah, John Shen, Gautham Chinya: Load balancing for multi-threaded applications via asymmetric power throttling. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 16, 2014: US08839258 (1 worldwide citation)

A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to t ...


9
Richard A Hankins, Gautham N Chinya, Hong Wang, David K Poulsen, Shirish Aundhe, Baiju V Patel, Sanjiv M Shah: Structured exception handling for application-managed thread units. Intel Corporation, Grossman Tucker Perreault & Pfleger PLLC, April 1, 2014: US08689215 (1 worldwide citation)

Methods, data structures, instructions, and techniques for structured exception handling for user-level threads in a multi-threading system are provided. Registered filter routines may be dispatched to a thread unit not managed by the operating system (OS). The dispatch may occur by allowing an OS-m ...


10
Hong Wang, Gautham N Chinya, Richard A Hankins, Shivnandan D Kaushik, Bryant Bigbee, Per Hammarlund, Xiang Zou, Jason W Brandt, Prashant Sethi, Douglas M Carmean, Baiju V Patel, John Shen, Scott Dion Rodgers, Ryan N Rakvic, John L Reid, David K Poulsen, Sanjiv M Shah, James Paul Held, James Charles Abel: Sequencer address management. Blakely Sokoloff Taylor & Zafman, October 5, 2006: US20060224858-A1

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses ...