1
David J Harriman, Brian K Langendorf, Jasmin Ajanovic: Method and apparatus for arbitrating between command streams. Intel Corporation, Jeffrey S Draeger, July 18, 2000: US06092158 (198 worldwide citation)

A method and apparatus for arbitrating between command streams. The method unblocks high priority commands which are blocked and then selects any remaining high priority commands. Normal priority commands are selected after the high priority commands. A memory controller described includes a command ...


2
Jasmin Ajanovic, Serafin Garcia, David J Harriman: Method and apparatus for initializing a computer interface. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 16, 2002: US06374317 (112 worldwide citation)

According to one embodiment, a computer system includes a first hub agent and a hub interface coupled to the first hub agent. The first hub agent is adaptable to sample the hub interface in order to detect the presence of a second hub agent upon initiation of the computer system. In a further embodi ...


3
David J Harriman: Method and apparatus for maintaining one or more queues of elements such as commands using one or more token queues. Intel Corporation, Jeffrey S Draeger, January 30, 2001: US06182177 (81 worldwide citation)

A method and apparatus for queuing commands. An apparatus of the present invention utilizes one or more token queues and a storage block to avoid maintaining multiple separate queues and/or to facilitate reordering of queued elements. The apparatus includes at least one token queue and a token assig ...


4
David J Harriman, Brain K Langendorf, Robert J Riesenman: System for issuing a command to a memory having a reorder module for priority commands and an arbiter tracking address of recently issued command. Intel Corportion, Leo V Novakoski, August 29, 2000: US06112265 (46 worldwide citation)

A system and method is provided for enhancing the efficiency with which commands from and initiating device to a resource are processed by the resource. The system includes a command queue, a plurality of command reorder slots coupled to the command queue, and command selection logic coupled to the ...


5
Brian K Langendorf, David J Harriman, Robert J Riesenman: System for delaying dequeue of commands received prior to fence command until commands received before fence command are ordered for execution in a fixed sequence. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 4, 2000: US06047334 (43 worldwide citation)

A method and apparatus for fencing the execution of commands. A fence command and an executable command are received in succession. The executable command is enqueued in a first queue together with an indication that the executable command succeeded the fence command. A synchronization value is enqu ...


6
David J Harriman, Maxim Dan: PCI express tunneling over a multi-protocol I/O interconnect. Intel Corporation, Schwabe Williamson & Wyatt P C, July 15, 2014: US08782321 (37 worldwide citation)

Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching ...


7
Jasmin Ajanovic, David J Harriman, David I Poisner: Method and apparatus for mode selection in a computer system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 21, 2003: US06636912 (35 worldwide citation)

According to one embodiment, a computer comprises a central processing unit (CPU), a first hub agent, a first hub interface coupled to the first hub agent, and a second hub agent coupled to the first hub interface. The first and second hub agents operate at a first data clocking rate determined by e ...


8
David J Harriman, Brian K Langendorf, Jasmin Ajanovic: Method and apparatus for improving system performance when reordering commands. Intel Corporation, Jeffrey S Draeger, July 11, 2000: US06088772 (31 worldwide citation)

A method and apparatus for ordering memory access commands. A command ordering circuit which is described includes a plurality of command slots which receive memory access commands. A page register stores a value indicating a last page accessed by a prior memory access command. Comparators compare t ...


9
Jasmin Ajanovic, David J Harriman: Method and apparatus for an improved interface between computer components. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 7, 2000: US06145039 (29 worldwide citation)

An interface to transfer data between a memory controller hub and an input/output (I/O) hub of a chipset within a computer system. One embodiment of the interface includes a bi-directional data signal path and a pair of source synchronous strobe signals. The data signal path transmits data in packet ...


10
Sridharan Ranganathan, Mahesh Wagh, David J Harriman: Providing a load/store communication protocol with a low power physical unit. Intel Corporation, Trop Pruner & Hu P C, May 21, 2013: US08446903 (28 worldwide citation)

In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a fi ...