1
David J Corisis: Semiconductor package. Micron Technology, Dickstein Shapiro Morin & Oshinsky, February 6, 2001: US06184465 (315 worldwide citation)

A semiconductor package is provided which includes a substrate having a plurality of semiconductor dice mounted thereon. The substrate is divided into segments by grooves formed in the bottom surface of the substrate. Each semiconductor die is electrically connected to the substrate by electrical co ...


2
David J Corisis, Jerry M Brooks, Walter L Moden: Stackable ball grid array package. Micron Technology, Trask Britt & Rossa, June 6, 2000: US06072233 (304 worldwide citation)

A stackable fine ball grid array (FBGA) package is disclosed that allows the stacking of one array upon another. This stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive ele ...


3
Walter L Moden, David J Corisis, Leonard E Mess, Larry D Kinsman: Stackable ceramic FBGA for high thermal applications. Micron Technology, TraskBritt, October 2, 2001: US06297548 (187 worldwide citation)

An apparatus package for high temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.


4
Leonard E Mess, David J Corisis, Walter L Moden, Larry D Kinsman: Apparatus and methods of packaging and testing die. Micron Technology, Dorsey & Whitney, September 25, 2001: US06294839 (173 worldwide citation)

Apparatus and methods of packaging and testing die. In one embodiment, a stacked die package includes a packaging substrate having a first surface with a recess disposed therein and a plurality of conductive leads coupled thereto, a first die attached to the packaging substrate within the recess and ...


5
David J Corisis: Lead frame including angle iron tie bar. Micron Technology, Killworth Gottman Hagan & Schaeff, October 16, 2001: US06303984 (158 worldwide citation)

A lead frame and method of making the same are provided. The lead frame includes a die mounting portion, first and second pairs of tie bars, and first and second tie bar bridges extending between respective second extension portions of each tie bar pair. First and second pairs of tie bars are mechan ...


6
David J Corisis: Semiconductor package having downset leadframe for reducing package bow. Micron Technology, Stephen A Gratton, May 8, 2001: US06229202 (154 worldwide citation)

A bow resistant semiconductor package includes a semiconductor die, a leadframe segment and a plastic body. The leadframe segment includes lead fingers attached and wire bonded to the die, and opposing volume equalizing members proximate to lateral edges of the die. The volume equalizing members are ...


7
David J Corisis: Stacked microelectronic dies and methods for stacking microelectronic dies. Micron Technology, Perkins Coie, August 19, 2003: US06607937 (151 worldwide citation)

An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the first packaged microelectronic devic ...


8
David J Corisis, Tracy Reynolds, Michael Slaughter, Daniel Cram, Leland R Nevill, Jerrold L King: Integrated circuit package including lead frame with electrically isolated alignment feature. Micron Technology, TraskBritt, June 12, 2001: US06246108 (148 worldwide citation)

An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature inc ...


9
David J Corisis, Brent Keeth: High speed IC package configuration. Micron Technology, Trask Britt & Rossa, August 15, 2000: US06103547 (143 worldwide citation)

Devices and methods for reducing lead inductance in integrated circuit (IC) packages. More specifically to an integrated circuit package configuration for high speed applications where the inductance of the leads is reduced or minimized in high capacity semiconductor device packages. The integrated ...


10
David J Corisis, Tracy Reynolds, Michael Slaughter, Daniel Cram, Leland R Nevill, Jerrold L King: Integrated circuit package alignment feature. Micron Technology, Trask Britt & Rossa, April 11, 2000: US06048744 (127 worldwide citation)

An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature inc ...



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