1
David B Kramer, David P Sonnier: Processor architecture and a method of processing. Agere Systems, October 3, 2006: US07116680 (15 worldwide citation)

A process and architecture to simplify the implementation of a high-speed scheduler. A traditional packet based scheduler works the length of the packet. Instead, the present invention uses a transmit queue that determines how many times a portion of a packet needs to be transmitted independent of t ...


2
Victor A Bennett, Leslie Zsohar, Shannon E Lawson, Sean W McGee, David P Sonnier, David B Kramer: Virtual reassembly system and method of operation thereof. Agere Systems, December 12, 2006: US07149211 (14 worldwide citation)

A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one pro ...


3
David B Kramer, Peter Williams: Locking mechanism for rack mounted devices. Cisco Technology, BainwoodHuang, December 14, 2010: US07850013 (8 worldwide citation)

A locking mechanism to minimize access to a portion of a rack-mounted electronic device is provided. The locking mechanism includes a bar supported at one end to a first vertical post of the rack, and a locking member supported at a second end of the bar for locking to a second vertical post. In one ...


4
David B Kramer, David P Sonnier: Processor with software-controlled programmable service levels. Agere Systems, May 8, 2007: US07215675 (6 worldwide citation)

A processor includes scheduling circuitry and a priority computation element associated with the scheduling circuitry. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, in accordance with a transmission priority established by the priority com ...


5
Victor A Bennett, Leslie Zsohar, Shannon E Lawson, Sean W McGee, David P Sonnier, David B Kramer: Virtual reassembly system and method of operation thereof. Agere Systems, February 1, 2005: US06850516 (5 worldwide citation)

A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one pro ...


6
Bryan D Marietta, David B Kramer, Gregory B Shippen: Method and apparatus for determining access permissions in a partitioned data processing system. Freescale Semiconductor, James L Clingan Jr, Joanna G Chiu, October 15, 2013: US08560782 (4 worldwide citation)

In a data processing system having a plurality of resources and plurality of partitions, each partition including one or more resources of the plurality of resources, a method includes receiving an access request to a target resource of the plurality of resources; using a first set of transaction at ...


7
David B Kramer, David P Sonnier: Processor with table-based scheduling using software-controlled interval computation. Agere Systems, July 17, 2007: US07245624 (3 worldwide citation)

A processor includes scheduling circuitry and an associated interval computation element. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, and is configured for utilization of at least one time slot table in scheduling the data blocks for tra ...


8
Asif Q Khan, David B Kramer: Link layer device with configurable address pin allocation. Agere Systems, January 2, 2007: US07159061 (3 worldwide citation)

Techniques are disclosed for flexible allocation of address pins of an interface bus to particular sub-buses of the interface bus. The interface bus is between at least one physical layer device and a link layer device in a communication system. Each of the sub-buses has an interface block of the li ...


9
Asif Q Khan, David B Kramer, David P Sonnier: Processor with scheduler architecture supporting multiple distinct scheduling algorithms. Agere Systems, January 13, 2009: US07477636 (3 worldwide citation)

A processor includes a scheduler operative to schedule data blocks for transmission from a plurality of queues or other transmission elements, utilizing at least a first table and a second table. The first table may comprise at least first and second first-in first-out (FIFO) lists of entries corres ...


10
Kun Xu, Tommi M Jokinen, David B Kramer: Message passing using direct memory access unit in a data processing system. Freescale Semiconductor, Mary Jo Bertani, Joanna G Chiu, December 24, 2013: US08615614 (3 worldwide citation)

A method includes generating, by a first software process of the data processing system, a source partition descriptor for a DMA job which requires access to a first partition of a memory which is assigned to a second software process of the data processing system and not assigned to the first softw ...