1
David A Webb Jr, Ricky C Hetherington, John E Murray, Tryggve Fossum, Dwight P Manley: Method and apparatus for ordering and queueing multiple memory requests. Digital Equipment Corporation, Arnold White & Durkee, June 22, 1993: US05222223 (81 worldwide citation)

In a pipelined computer system 10, memory access functions (requests) are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the inst ...


2
David A Webb Jr, David B Fite, Ricky C Hetherington, Francis X McKeen, Mark A Firstenberg, John E Murray, Dwight P Manley, Ronald M Salett, Tryggve Fossum: System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer. Digital Equipment Corporation, Arnold White & Durkee, January 15, 1991: US04985825 (77 worldwide citation)

A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access ...


3
Ricky C Hetherington, Tryggve Fossum, Maurice B Steinman, David A Webb Jr: Write back buffer with error correcting capabilities. Digital Equipment Corporation, Arnold White & Durkee, February 19, 1991: US04995041 (47 worldwide citation)

In the operation of high-speed computers, it is frequently advantageous to employ a high speed cache memory within each CPU of a multiple CPU computer system. A standard, slower memory configuration remains in use for the large, common main memory, but those portions of main memory which are expecte ...


4
Ricky C Hetherington, David A Webb Jr, David B Fite, John E Murray, Tryggve Fossum, Dwight P Manley: System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation. Digital Equipment Corporation, Richard J Paciulan, Denis G Maloney, September 20, 1994: US05349651 (31 worldwide citation)

In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different prog ...


5
John E Murray, Mark A Firstenberg, David B Fite, Michael M McKeon, Wiliam R Grundmann, David A Webb Jr, Ronald M Salett, Tryggve Fossum, Dwight P Manley, Ricky C Hetherington: System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register. Digital Equipment Corporation, Arnold White & Durkee, August 25, 1992: US05142631 (25 worldwide citation)

A method is provided for preprocessing multiple instructions prior to execution of such instructions in a digital computer having an instruction decoder, an instruction execution unit, and multiple general purpose registers which are read to produce memory addresses during the preprocessing. The met ...


6
David A Webb Jr, Ricky C Hetherington, Ronald M Salett, Trvggve Fossum, Dwight P Manley: Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width. Digital Equipment Corporation, Arnold White & Durkee, May 28, 1991: US05019965 (20 worldwide citation)

In a computer system, the flow of data from the execution unit to the cache 28 is enhanced by pairing individual, sequential longword write operations into a simultaneous quadword write operation. Primary and secondary writebuffers 50, 52 sequentially receive the individual longwords during first an ...


7
Rahul Razdan, David A Webb Jr, James B Keller, Derrick R Meyer: Method and apparatus for a dedicated physically indexed copy of the data cache tag arrays. Compaq Computer Corporation, Hamilton Brook Smith & Reynolds P C, June 26, 2001: US06253301 (3 worldwide citation)

A data caching system and method includes a data store for caching data from a main memory, a primary tag array for holding tags associated with data cached in the data store, and a duplicate tag array which holds copies of the tags held in the primary tag array. The duplicate tag array is accessibl ...