1
Gregory C Edgington, Joseph C Circello, Daniel M McCarthy, Richard Duerden: Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes. Motorola, Keith E Witek, June 25, 1996: US05530804 (95 worldwide citation)

A processor (10) has two modes of operation. One mode of operation is a normal mode of operation wherein the processor (10) accesses user address space or supervisor address space to perform a predetermined function. The other mode of operation is referred to as a debug, test, or emulator mode of op ...


2
Hiroaki Fukumaru, Siochi Takaya, Yoshihiro Miyazaki, Daniel M McCarthy: Data processing device with common memory connecting mechanism. Hitachi, Arix Computer, Antonelli Terry Stout & Kraus, January 4, 1994: US05276836 (72 worldwide citation)

A data processing device which includes a common memory connecting mechanism which is located between a memory bus to which copyback cache is connected, and a common memory. The common memory connecting mechanism includes a slave type transfer mechanism which directly assesses the common memory bypa ...


3
Daniel M McCarthy, Joseph C Circello, Gabriel R Munguia, Nicholas J Richardson: Coherent cache structures and methods. Edgcore Technology, Cahill Sutton & Thomas, May 22, 1990: US04928225 (63 worldwide citation)

A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly ...


4
Daniel M McCarthy, Joseph C Circello, Gabriel R Munguia, Nicholas J Richardson: Coherent cache structures and methods. Edge Computer Corporation, Cahill Sutton & Thomas, July 2, 1991: US05029070 (60 worldwide citation)

A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly ...


5
William B Ledbetter Jr, Daniel M McCarthy, James G Gay: Integrated circuit having a control signal for identifying coinciding active edges of two clock signals. Motorola, Keith E Witek, January 16, 1996: US05485602 (28 worldwide citation)

A data processing system receives a CLK signal for performing operations internal to a data processor (10). The data processor (10) has a CPU (12) which performs operations in response to the CLK signal. The bus is allowed to operate at a frequency which is less than or equal to the operational freq ...


6
Joseph C Circello, Daniel M McCarthy, Sylvia M Thirtle: Data processor device having trace capabilities and method. Freescale Semiconductor, November 13, 2012: US08312253 (27 worldwide citation)

In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to allow the trace buffer information to be accessed at an external interface to the integrated circuit devi ...


7
Daniel M McCarthy, Paul W Hollis, Ruey J Yu, Renny L Eisele: Scan based path delay testing of integrated circuits containing embedded memory elements. Motorola, Bruce E Hayden, Craig J Yudell, June 2, 1998: US05761215 (24 worldwide citation)

Accurate delay testing of integrated circuits containing memory arrays embedded in combinational logic utilizes actual memory array timing. Actual memory timing signals provide the timing for bypassing the memory in SCAN Mode. The result is that simulated memory accesses during SCAN Mode testing hav ...


8
Daniel M McCarthy, Joseph C Circello, Richard Duerden, Gregory C Edgington, Cliff L Parrott, William B Ledbetter Jr: Data processing system for performing either a precise memory access or an imprecise memory access based upon a logical address value and method thereof. Motorola, Keith E Witek, September 9, 1997: US05666509 (21 worldwide citation)

A processor (10) has a data cache unit (16) wherein the data cache unit includes a memory management unit (MMU) (32). The MMU contains memory locations within transparent translation registers (TTRs), an address translation cache (40), or a table walk controller (42) which store or generate cache mo ...


9
Daniel M McCarthy: Merge control apparatus for a store into cache of a data processing system. Honeywell Information Systems, A A Sapelli, J S Solakian, July 14, 1987: US04680702 (18 worldwide citation)

A register unit includes means for storing pertinent data relative to a plurality of cache transactions, identifying the zones of an addressed word block which is the subject of the individual transactions. These data are selectively extracted from the register to control the merging of the identifi ...


10
Joseph C Circello, Daniel M McCarthy: Performance monitor with precise start-stop control. Freescale Semiconductor, Ingrassia Fisher & Lorenz P C, October 7, 2008: US07433803 (8 worldwide citation)

A system and method for performance monitoring in processors is provided. The system and method evaluates the performance of the processor by counting selected events during one or more defined periods. The performance monitor provides improved performance characterization by providing highly-config ...