1
G Glenn Henry, Arturo Martin de Nicolas, Daniel G Miner: Fuse array control for smart function enable. Integrated Device Technology, James W Huffman, March 30, 1999: US05889679 (79 worldwide citation)

An apparatus and method for smart configuration of functional blocks within a semiconductor device is provided. A fuse array contains a plurality of fuses that are blown in manufacturing to enable/disable functional blocks on the semiconductor device. A control unit reads the state of the fuses, and ...


2
Daniel G Miner: Apparatus for testing memory in a microprocessor. IP First, Richard K Huffman, James W Huffman, April 9, 2002: US06370661 (24 worldwide citation)

An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters prov ...


3
Daniel G Miner: Apparatus and method for testing memory in a microprocessor. IP First, Richard K Huffman, James W Huffman, March 1, 2005: US06862704 (16 worldwide citation)

An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters prov ...


4
Daniel G Miner: Apparatus and method for testing memory in a microprocessor. IP First, Richard K Huffman, James W Huffman, December 10, 2002: US06493839 (16 worldwide citation)

An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters prov ...


5
Daniel G Miner, Brian Snider: Method and apparatus for wafer test of redundant circuitry. Integrated Device Technology, James W Huffman, November 10, 1998: US05835431 (4 worldwide citation)

A method and apparatus for testing redundant circuitry within a memory array is provided. A control unit is described to interface a memory array to a wafer tester to selectively enable redundant rows/columns within a memory array during wafer test, without requiring permanent alteration of row/colu ...