1
Daniel C Guterman, Yupin Kawing Fong: Multi-state memory. Sandisk Corporation, Steven F Caserza, Flehr Hohbach Test Albritton & Herbert, April 24, 2001: US06222762 (945 worldwide citation)

Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog tec ...


2
Daniel C Guterman, Gheorghe Samachisa, Yupin K Fong, Eliyahou Harrai: EEPROM with split gate source side injection. Sundisk Corporation, Steven F Caserza, May 17, 1994: US05313421 (580 worldwide citation)

Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organiz ...


3
Jack H Yuan, Gheorghe Samachisa, Daniel C Guterman, Eliyahou Harari: Dense vertical programmable read only memory cell structure and processes for making them. SunDisk Corporation, Majestic Parsons Siebert & Hsue, August 30, 1994: US05343063 (522 worldwide citation)

A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are forme ...


4
Daniel L Auclair, Jeffrey Craig, John S Mangan, Robert D Norman, Daniel C Guterman, Sanjay Mehrotra: Soft errors handling in EEPROM devices. SanDisk Corporation, Majestic Parsons Siebert & Hsue, August 12, 1997: US05657332 (492 worldwide citation)

Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulativ ...


5
Daniel L Auclair, Jeffrey Craig, John S Mangan, Robert D Norman, Daniel C Guterman, Sanjay Mehrotra: Soft errors handling in EEPROM devices. SanDisk Corporation, Majestic Parsons Siebert & Hsue, July 2, 1996: US05532962 (400 worldwide citation)

Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulativ ...


6
Eliyahou Harari, Daniel C Guterman, Sanjay Mehrotra, Stephen J Gross: Method for optimum erasing of EEPROM. SunDisk Corporation, Majestic Parsons Siebert & Hsue, December 14, 1993: US05270979 (361 worldwide citation)

Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques include a 2-phase verification process interleavi ...


7
Eliyahou Harari, Daniel C Guterman, Robert F Wallace: Removable mother/daughter peripheral card. SanDisk Corporation, Majestic Parsons Siebert & Hsue, March 23, 1999: US05887145 (262 worldwide citation)

A peripheral card having a Personal Computer ("PC") card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost fla ...


8
Daniel C Guterman, Gheorghe Samachisa, Yupin Kawing Fong: EEPROM with split gate source side injection. Sundisk Corporation, Steven F Flehr Hohbach Test Albritton & Herbert Caserza, January 27, 1998: US05712180 (248 worldwide citation)

Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organiz ...


9
Daniel C Guterman, Stephen Jeffrey Gross, Geoffrey S Gongwer: Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data. SanDisk Corporation, Parsons Hsue & de Runtz, June 15, 2004: US06751766 (235 worldwide citation)

The quality of data stored in a memory system is assessed by different methods, and the memory system is operated according to the assessed quality. The data quality can be assessed during read operations. Subsequent use of an Error Correction Code can utilize the quality indications to detect and r ...


10
Eliyahou Harari, Daniel C Guterman, George Samachisa, Jack H Yuan: Dual floating gate EEPROM cell array with steering gates shared by adjacent cells. SanDisk Corporation, Majestic Parsons Siebert & Hsue, November 21, 2000: US06151248 (231 worldwide citation)

An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the ...