1
Vladimir Mikhalev, Aaron M Schoenfeld, Daniel B Penney, William C Waldrop: Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers. Micron Technology, Dorsey & Whitney, August 12, 2003: US06605969 (56 worldwide citation)

A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operat ...


2
Jason M Brown, Daniel B Penney: Data-strobe input buffers for high-frequency SDRAMS. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, August 28, 2001: US06282132 (16 worldwide citation)

A device is discussed that enables an input buffer to recognize the first rising edge of a strobe so as to validate data. In one embodiment, a method for enabling recognition of valid data in a DDR SDRAM is discussed. The method includes analyzing memory commands before a setup time is expired, and ...


3
Vladimir Mikhalev, Aaron M Schoenfeld, Daniel B Penney, William C Waldrop: Method and circuit for adjusting the timing of output data based on an operational mode of output drivers. Micron Technology, Dorsey & Whitney, February 17, 2004: US06693472 (14 worldwide citation)

A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operat ...


4
Vladimir Mikhalev, Aaron M Schoenfeld, Daniel B Penney, William C Waldrop: Method and circuit for adjusting the timing of output data based on an operational mode of output drivers. Micron Technology, Dorsey & Whitney, December 13, 2005: US06975149 (10 worldwide citation)

A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operat ...


5
Vladimir Mikhalev, Aaron M Schoenfeld, Daniel B Penney, William C Waldrop: Method and circuit for adjusting the timing of output data based on an operational mode of output drivers. Micron Technology, Dorsey & Whitney, November 16, 2004: US06819151 (10 worldwide citation)

A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operat ...


6
Brian J Ladner, Daniel B Penney: Memory device having programmable column segmentation to increase flexibility in bit repair. Micron Technology, Dickstein Shapiro Morin & Oshinsky, September 7, 2004: US06788597 (9 worldwide citation)

A method and apparatus for programmable column segmentation of a memory device is disclosed. The method and apparatus provide different programmable selected column segmentation arrangements to provide more flexibility in primary column repair of a memory device.


7
Brian J Ladner, Daniel B Penney: Memory device having programmable column segmentation to increase flexibility in bit repair. Micron Technology, Dickstein Shapiro Morin & Oshinsky, April 22, 2003: US06552937 (8 worldwide citation)

A method and apparatus for programmable column segmentation of a memory device is disclosed. The method and apparatus provide different programmable selected column segmentation arrangements to provide more flexibility in primary column repair of a memory device.


8
Daniel B Penney: Predecode column architecture and method. Micron Technology, Dorsey & Whitney, August 3, 2004: US06771557 (6 worldwide citation)

A system and method for predecoding memory addresses by generating a sequence of predecode signals based on the memory address, providing the sequence of predecode signals as a first set of activation signals, and based on the value of the memory address, either resequencing the sequence of predecod ...


9
Daniel B Penney, Jason M Brown, Frank Alejano: High speed column redundancy scheme. Texas Instruments Incorporated, Robby T Holland, Carlton H Hoel, Frederick J Telecky Jr, August 1, 2000: US06097645 (5 worldwide citation)

A redundancy circuit (300) for generating a standard column access signal (STD) and a redundant column access signal (RED) is disclosed. A modified NOR-type decoder (310) determines if an applied address is the same as a defective address. In the event the applied address is the same as the defectiv ...


10