1
Daniel A Boudreau, James M Sandini, Edward R Salas: Lockout operation among asynchronous accessers of a shared computer system resource. Honeywell Information Systems, William A Linnell, George Grayson, John S Solakian, May 6, 1986: US04587609 (113 worldwide citation)

A data processing system having a plurality of units includes a shareable unit which is shareable between two or more of the other units. Lock apparatus is provided in the shareable unit to allow a first unit to lock the shareable unit so that no other unit attempting to lock the shareable unit will ...


2
Daniel A Boudreau: Data processing system common bus utilization detection logic. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, March 5, 1985: US04503495 (54 worldwide citation)

A common bus utilization detection logic that is used when a particular device connected to a common bus has been granted access to the common bus wherein bus access is granted on a priority basis. By positioning the bus utilization logic in priority positions on the common bus adjacent to the parti ...


3
Daniel A Boudreau: Data processing system auto address development logic for multiword fetch. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, April 16, 1985: US04511960 (50 worldwide citation)

An auto address development logic that, when provided a starting address, is used to develop consecutive addresses as multiple words of information are presented, one word at a time, during multiple consecutive information transfer cycles. The logic retains for use a current address while simultaneo ...


4
Daniel A Boudreau, Edward R Salas: Priority resolver having dynamically adjustable priority levels. Honeywell Information Systems, William A Linnell, Nicholas Prasinos, January 8, 1985: US04493036 (50 worldwide citation)

A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main ...


5
Edward R Salas, Edwin P Fisher, Robert B Johnson, Chester M Nibby Jr, Daniel A Boudreau: Memory identification apparatus and method. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, October 1, 1985: US04545010 (45 worldwide citation)

A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and a ...


6
Daniel A Boudreau, Edward R Salas: Technique for determining maximum physical memory present in a system and for detecting attempts to access nonexistent memory. Honeywell Bull, William A Linnell, George Grayson, John S Solakian, November 22, 1988: US04787060 (33 worldwide citation)

A method for determining the maximum amount of physical memory present in a data processing system that can be configured to have one or more memory modules where the memory modules may be one of several types having different amounts of memory locations. By having signals indicating the presence of ...


7
Daniel A Boudreau, Edward R Salas: Asynchronous multiport parallel access memory system for use in a single board computer system. Honeywell Information Systems, Faith F Driscoll, John S Solakian, March 31, 1987: US04654788 (23 worldwide citation)

A data processing system includes an asynchronous parallel multiport volatile main memory system accessible directly by any one of M number of central processing units or by I/O controllers connected in common to any one of N number of system buses. Priority resolver circuits award access to main me ...


8
Mark L Smith, Joseph J Nicosia, Daniel A Boudreau, Leo A Goyette: Redundant repeater. Xyplex, Fish & Richardson, August 14, 1990: US04949340 (16 worldwide citation)

A redundant repeater connected between two transmission mediums that can operate in a repeat state where packets are repeated between the mediums, and a standby state where no packets are repeated and where the repeater determines whether packets are being properly repeated between the transmission ...


9
Daniel A Boudreau, Edward R Salas: Priority resolver with lowest priority level having shortest logic path. Honeywell Information Systems, William A Linnell, George Grayson, John S Solakian, July 15, 1986: US04600992 (14 worldwide citation)

A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main ...


10
Daniel A Boudreau, Edward R Salas, Richard C Zelley: Memory architecture for facilitating optimum replaceable unit (ORU) detection and diagnosis. Honeywell Information Systems, Faith F Driscoll, John S Solakian, January 7, 1986: US04563736 (14 worldwide citation)

A single computer board data processing system includes a multiport memory system which is accessible by I/O controllers through a system bus I/O memory port or directly by the system's central processing unit (CPU) via a CPU memory port. The logic and control circuits of the memory ports and CPU ar ...