1
D Michael Bell, Mark A Gonzales, Susan S Meredith: Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 13, 1996: US05546546 (120 worldwide citation)

A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a de ...


2
Stephen S Pawlowski, Peter D MacWilliams, D Michael Bell: Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system. Intel Corporation, Kenyon & Kenyon, May 18, 1999: US05905876 (93 worldwide citation)

A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlo ...


3
D Michael Bell: PCI split transactions utilizing dual address cycle. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 14, 1997: US05594882 (77 worldwide citation)

A scheme for providing split transaction capability on a PCI standard bus without modification to the existing PCI standard. Additional address bits are provided to a standard PCI address signal. The additional bits carry information regarding the requestor of a read transaction. By providing the re ...


4
D Michael Bell, Mark A Gonzales, Susan S Meredith: Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 9, 1996: US05535340 (71 worldwide citation)

A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Decoding circuitry within the bridge issues a deferred r ...


5
D Michael Bell: Bootstrap loading from external memory including disabling a reset from a keyboard controller while an operating system load signal is active. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 25, 1995: US05410707 (59 worldwide citation)

A computer system bootstrap loads a processor and associated memory from an external memory device instead of being bootstrap loaded from on-board read only memory. The computer system is comprised of a system bus, a processing component, a first system memory device, a memory card interface control ...


6
D Michael Bell: Synchronous/asynchronous clock net with autosense. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 18, 1995: US05434996 (56 worldwide citation)

A circuit within a bus bridge operating in a first clock domain and a second clock domain, wherein the circuit allows data, address or any other information to be reliably transferred between the first and second clock domains regardless whether or not an internal bus clock of the second clock domai ...


7
D Michael Bell, Mark A Gonzales, Susan S Meredith: Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 1, 2000: US06021451 (51 worldwide citation)

A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a de ...


8
D Michael Bell: Hot plug connected I/O bus for computer system. Intel Corporation, Antonelli Terry Stout & Kraus, May 30, 2000: US06070207 (46 worldwide citation)

A computer system includes a host processor coupled to a host bus. The computer system also includes a memory system coupled to the host bus, and an I/O bridge controller coupled to the host bus and including a plurality of ports. An I/O bus bridge is provided that is hot plug connectable to at leas ...


9
D Michael Bell: System and method of flow control for a high speed bus. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 22, 2000: US06108736 (22 worldwide citation)

A system and method for controlling the flow of information between devices. A count is maintained representative of requests issued by a first device. The count is incremented for each packet issued by a first device and decremented for each packet received at the first device. A maximum buffer cou ...


10
D Michael Bell, Mark A Gonzales, Susan S Meredith: Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 10, 1998: US05835739 (22 worldwide citation)

A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a de ...