1
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Richard E Perego, David Nguyen, Billy W Garrett Jr, Ely Tsern, Craig E Hampel, Wai Yeung Yip: Multiple channel modules and bus systems using same. Rambus, July 20, 2004: US06765800 (46 worldwide citation)

Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.


2
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Richard E Perego, David Nguyen, Billy W Garrett Jr, Ely Tsern, Craig E Hampel, Wai Yeung Yip: Multiple channel modules and bus systems using same. Rambus, Hunton & Williams, May 24, 2005: US06898085 (37 worldwide citation)

Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.


3
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Richard E Perego, David Nguyen, Billy W Garrett, Ely Tsern, Craig E Hampel, Wai Yeung Yip: Multiple Channel Modules and Bus Systems Using Same. Rambus, Hunton & Williams Rambus, May 31, 2007: US20070120575-A1

Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.


4
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Richard E Perego, David Nguyen, Billy W Garrett, Ely Tsern, Craig E Hampel, Wai Yeung Yip: Multiple channel modules and bus systems using same. Rambus, Ross D Snyder & Associates, December 20, 2001: US20010053069-A1

Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.


5
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Richard E Perego, David Nguyen, Billy W Garrett, Ely Tsern, Craig E Hampel, Wai Yeung Yip: Multiple channel modules and bus systems using same. Rambus, Hunton & Williams Rambus, June 30, 2005: US20050142950-A1

Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.


6
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Richard E Perego, David Nguyen, Billy W Garrett, Ely Tsern, Craig E Hampel, Wai Yeung Yip: Multiple channel modules and bus systems using same. Rambus, Thomas E Anderson, Hunton & Williams, June 3, 2004: US20040105240-A1

Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.


7
Mark A Horowitz, Richard M Barth, Craig E Hampel, Alfredo Moncayo, Kevin S Donnelly, Jared L Zerbe: Apparatus and method for topography dependent signaling. Rambus, November 20, 2001: US06321282 (223 worldwide citation)

Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter, a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topo ...


8
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen, Thomas J Holman, Andrew V Anderson, Peter D MacWilliams: High performance cost optimized memory with delayed memory writes. Rambus Incorporated, Intel Corporation, Pennie & Edmonds, June 13, 2000: US06075730 (134 worldwide citation)

A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core wr ...


9
Ely K Tsern, Richard M Barth, Craig E Hampel, Donald C Stark: Power control system for synchronous memory device. Rambus, Gary S Williams, Pennie & Edmonds, March 2, 2004: US06701446 (116 worldwide citation)

A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the m ...


10
Richard M Barth, Ely K Tsern, Craig E Hampel, Frederick A Ware, Todd W Bystrom, Bradley A May, Paul G Davis: Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain. Rambus, Blakely Sokoloff Taylor & Zafman, November 28, 2000: US06154821 (114 worldwide citation)

A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memo ...