1
Craig C Hansen, Timothy B Robinson, Alan G Corry: DRAM with high bandwidth interface that uses packets and arbitration. Microunity Systems Engineering, McDermott Will & Emery, July 7, 1998: US05778419 (245 worldwide citation)

A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates. The memory chip includes a memory device and an interface capable of achieving high bandwidth throughput. The memory device decodes, arbitrates between, and executes memory access co ...


2
Craig C Hansen, John Moussouris: General purpose, dynamic partitioning, programmable media processor. MicroUnity Systems Engineering, McDermott Will & Emery, December 21, 1999: US06006318 (120 worldwide citation)

A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data through ...


3
Craig C Hansen, Henry Massalin: Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction. Microunity Engeering Systems, McDermott Will & Emery, September 14, 1999: US05953241 (117 worldwide citation)

A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the ...


4
Craig C Hansen, Thomas J Riordan: RISC computer with unaligned reference handling and method for the same. Mips Computer Systems, Kenyon & Kenyon, March 21, 1989: US04814976 (114 worldwide citation)

In a RISC device a set of four instructions are provided which allow either the loading or the storage of an unaligned reference. The instructions are overlapped to reduce the overall execution time of the device. A circuit is also provided for executing the instruction set.


5
Larry B Weber, Craig C Hansen, Thomas J Riordan, Steven A Przybylski: Dual byte order computer architecture a functional unit for handling data sets with differnt byte orders. Mips Computer Systems, Kenyon & Kenyon, September 25, 1990: US04959779 (81 worldwide citation)

A CPU or other function unit is disclosed which follows one data ordering scheme internally, and in which incoming and/or outgoing data pass through a data order conversion unit for adapting it to a selectable external data ordering scheme. The means for specifying the external data ordering scheme ...


6
Craig C Hansen: Method and system for facilitating byte ordering interfacing of a computer system. Microunity Systems Engineering, Burns Doane Swecker & Mathis L, October 6, 1998: US05819117 (69 worldwide citation)

A method and data processing system for transferring data between the system and a memory system using more than one byte ordering convention by incorporating byte order information into instruction codes. The byte order information is coupled to a control unit along with other information character ...


7
Craig C Hansen, Henry Massalin: Multiplier array processing system with enhanced utilization at lower precision. Microunity Systems Engineering, McDermott Will & Emery, June 24, 2003: US06584482 (69 worldwide citation)

A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the ...


8
Craig C Hansen: Technique of incorporating floating point information into processor instructions. MicroUnity Systems Engineering, Burns Doane Swecker & Mathis L, September 22, 1998: US05812439 (66 worldwide citation)

A floating point system and method employing instructions where instruction have incorporated floating point information. The floating point information indicates whether an exception trap should occur and the type of rounding to be performed upon "inexact" arithmetic results. The floating point inf ...


9
Craig C Hansen, John G Campbell, Timothy B Robinson: Accessing system that reduces access times due to transmission delays and I/O access circuitry in a burst mode random access memory. MicroUnity Systems Engineering, Burns Doane Swecker & Mathis, April 25, 1995: US05410670 (61 worldwide citation)

A large burst mode memory accessing system includes N discrete sub-memories and three main I/O ports. Data is stored in the sub-memories so that the sub-memories are accessed depending on their proximity to the main I/O ports. Three parallel pipelines provide a data path to/from the main I/O ports a ...


10
Craig C Hansen: Method and apparatus for precise floating point exceptions. MIPS Computer Systems, Townsend and Townsend, November 7, 1989: US04879676 (49 worldwide citation)

In data processing systems of the type operable to perform floating point computations there is provided a method, and apparatus implementing that method, for predicting, in advance of the floating point computation, whether or not the computation will produce a floating point exception (e.g., overf ...