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Akaogi Takao, Al Shamma Ali K, Cleveland Lee Edward, Kim Yong, Lin Jin Lien, Teh Boon Tang, Nguyen Kendra: Voltage boost level clamping circuit for a flash memory. Advanced Micro Devices, Fujitsu, sRODDY Richard J, August 9, 2001: WO/2001/057874

A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (V¿CC?) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage ...


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Akaogi Takao, Nguyen Kendra, Cleveland Lee Edward: Multiple bank simultaneous operation for a flash memory. Advanced Micro Devices, Fujitsu, sRODDY Richard J, September 20, 2001: WO/2001/069603

An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write ope ...


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Lin Jin Lien, Akaogi Takao, Al Shamma Ali K, Cleveland Lee Edward, Kim Yong, Teh Boon Tang, Nguyen Kendra: Command-driven test modes. Advanced Micro Devices, Fujitsu, sRODDY Richard J, August 16, 2001: WO/2001/059571

A system and a method for selectively placing a computer memory device (100), even when its data/address pins (104) are multiplexed, into a special test mode. In order to allow the manufacturer of a memory device to selectively enter into one of a plurality of special high-speed tests, while prevent ...


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Akaogi Takao, Al Shamma Ali K, Cleveland Lee Edward, Kim Yong, Lin Jin Lien, Teh Boon Tang, Nguyen Kendra: Voltage boost level clamping circuit for a flash memory. Advanced Micro Devices, Fujitsu, November 6, 2002: EP1254459-A2

A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (VCC) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage b ...


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Akaogi Takao, Nguyen Kendra, Cleveland Lee Edward: Multiple bank simultaneous operation for a flash memory. Advanced Micro Devices, Fujitsu, December 18, 2002: EP1266377-A2

An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write ope ...


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Akaogi Takao, Al Shamma Ali K, Cleveland Lee Edward, Kim Yong, Lin Jin Lien: Voltage boost level clamping circuit for a flash memory. Advanced Micro Devices, Fujitsu, January 1, 2003: TW516031

A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (VCC) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage b ...


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Akaogi Takao, Nguyen Kendra, Cleveland Lee Edward: Multiple bank simultaneous operation for a flash memory. Spansion, February 17, 2003: KR1020027012128

An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write ope ...


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Akaogi Takao, Al Shamma Ali K, Cleveland Lee Edward, Kim Yong, Lin Jin Lien, Teh Boom Tang, Nguyen Kendra: Voltage boost level clamping circuit for a flash memory. Spansion, February 17, 2003: KR1020027009833

A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (VCC) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage b ...